Details, datasheet, quote on part number: Z8S18020PEC
DescriptionEnhanced Z180 Microprocessor
CompanyZilog, Inc.
DatasheetDownload Z8S18020PEC datasheet
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Features, Applications


Code Compatible with Zilog Z80® CPU Extended Instructions Two Chain-Linked DMA Channels Low Power-Down Modes On-Chip Interrupt Controllers Three On-Chip Wait-State Generators On-Chip Oscillator/Generator Expanded MMU Addressing (up to 1 MB) Clocked Serial I/O Port

Two 16-Bit Counter/Timers Two Enhanced UARTs (up to 512 Kbps) Clock Speeds: MHz Operating Range: (3.3V@ 20 MHz) Operating Temperature Range: to +85°C Extended Temperature Range Three Packaging Styles ­ 68-Pin PLCC ­ 64-Pin DIP ­ 80-Pin QFP

The enhanced Z80180/Z8S180/Z8L180TM significantly improves on the previous Z80180 models while still providing full backward compatibility with existing Zilog Z80 devices. The Z80180/Z8S180/Z8L180 now offers faster execution speeds, power saving modes, and EMI noise reduction. This enhanced Z180 design also incorporates additional feature enhancements to the ASCIs, DMAs, and Icc STANDBY Mode power consumption. With the addition of "ESCC-like" Baud Rate Generators (BRGs), the two ASCIs now have the flexibility and capability to transfer data asynchronously at rates to 512 Kbps. In addition, the ASCI receiver has added a 4-byte First In First Out (FIFO) which can be used to buffer incoming data to reduce the incidence of overrun errors. The DMAs have been modified to allow for a "chain-linking" of the two DMA channels when set to take their DMA requests from the same peripherals device. This feature allows for non-stop DMA operation between the two DMA channels, reducing the amount of CPU intervention (Figure 1). Not only does the Z80180/Z8S180/Z8L180 consume less power during normal operations than the previous model, it has also been designed with three modes intended to further reduce the power consumption. Zilog reduced Icc power consumption during STANDBY Mode to a minimum µA by stopping the external oscillators and internal clock. The SLEEP mode reduces power by placing the CPU into a "stopped" state, thereby consuming less current while the on-chip I/O device is still operating. The SYSTEM STOP mode places both the CPU and the onchip peripherals into a "stopped" mode, thereby reducing power consumption even further. A new clock doubler feature has been implemented in the Z80180/Z8S180/Z8L180 device that allows the programmer to double the internal clock from that of the external clock. This provides a systems cost savings by allowing the use of lower cost, lower frequency crystals instead of the higher cost, and higher speed oscillators. The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages. DS971800401 PRELIMINARY 1-1

Z80180/Z8S180/Z8L180 Enhanced Z180 Microprocessor Notes: All Signals with a preceding front slash, are active Low, for example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Alternatively, an overslash may be used to signify active Low, for example WR

Zilog Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS



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