Details, datasheet, quote on part number: Z8L18020FSC
PartZ8L18020FSC
CategoryMicroprocessors
DescriptionCore / Cpu Used  = Z180 ;; External Memory  = 1 ;; Speed  = 20 ;; I/O  = Clock Serial ;; Timers  = 2 ;; Communications Controller  = Csio, Uart ;; Other Features  = 1MB Mmu, 2xDMA's, 2xUARTs, 3.3V Operation ;;
CompanyZilog, Inc.
DatasheetDownload Z8L18020FSC datasheet
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Features, Applications

Code Compatible with ZiLOG Z80 CPU Extended Instructions Two Chain-Linked DMA Channels Low Power-Down Modes On-Chip Interrupt Controllers Three On-Chip Wait-State Generators On-Chip Oscillator/Generator Expanded MMU Addressing (Up to 1 MB) Clocked Serial I/O Port Two 16-Bit Counter/Timers Two Enhanced UARTs (up to 512 Kbps) Clock Speeds: 20, 33 MHz Operating Range: (3.3V@ 20 MHz) Operating Temperature Range: to +85C Extended Temperature Range Three Packaging Styles 68-Pin PLCC 64-Pin DIP 80-Pin QFP

The enhanced Z8S180/Z8L180TM significantly improves on previous Z80180 models, while still providing full backward compatibility with existing ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving modes, and EMI noise reduction. This enhanced Z180TM design also incorporates additional feature enhancements to the ASCIs, DMAs, and 56#0&$; mode power consumption. With the addition of ESCC-like Baud Rate Generators (BRGs), the two ASCIs offer the flexibility and capability to transfer data asynchronously at rates to 512 Kbps. In addition, the ASCI receiver features a 4-byte first in/first out (FIFO) buffer which reduces the likelihood of overrun errors. The DMAs have been modified to allow for chain-linking of the two DMA channels when set to take their DMA requests from the same peripherals device. This feature allows for nonstop DMA operation between the two DMA channels. Not only does the Z8S180/Z8L180 consume less power during normal operations than the previous model, it offers three modes intended to further reduce power consumption. Power consumption during 56#0&$; Mode is reduced A by stopping the external oscillators and internal clock. The 5.''2 mode reduces power by placing the CPU into a stopped state, consuming less current while the onchip I/O devices still operate. The 5;56'/ 5612 mode places both the CPU and the on-chip peripherals into a stopped mode, reducing power consumption even further. A new clock-doubler feature in the Z8S180/Z8L180 allows the internal clock speed to be twice the external clock speed. As a result, system cost is reduced by allowing the use of lower-cost, lower-frequency crystals. The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages.

0QVG All Signals with an overline are active Low. For example: B/W, in which WORD is active Low; or B/W, in which BYTE is active Low.

Power connections follow the conventional descriptions below:


 

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