Details, datasheet, quote on part number: W49L201S-90
CategoryMemory => Flash
Description128k X 16 CMOS Flash Memory
CompanyWinbond Electronics Corp America
DatasheetDownload W49L201S-90 datasheet


Features, Applications

The 2-megabit, 5-volt only CMOS flash memory organized 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F201 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers.


Single 5-volt operations: - 5-volt Read/Erase/Program Fast Program operation: - Word-by-Word programming: 50 S (max.) Fast Erase operation: 60 mS (typ.) Fast Read access time: 45/55 nS Endurance: 1K/10K cycles (typ.) Ten-year data retention Hardware data protection Sector configuration - One 8K words boot block with lockout protection - Two 8K words parameter blocks - One 104K words (208K bytes) Main Memory Array Blocks

Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.)

Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling

Latched address and data TTL compatible I/O JEDEC standard word-wide pinouts Available packages: 44-pin SOP, 48-pin TSOP


RESET OE WE VDD GND NC Reset Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection

The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data to the output pins. The data bus is in high impedance state when either OE is high. Refer to the timing waveforms for further details.

The RESET input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts the device and all outputs are at high impedance state. The device also resets the internal state machine to read array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to assure data integrity. As the high state re-asserted to the RESET pin, the device will return to read or standby mode, it depends on the control signals. The system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled.

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words of the memory with the address range from to 1FFF(hex). See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once the RESET pin returns to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 8K-words block, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data is "1", the boot block programming lockout feature is activated; if the output data is "0", the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be Publication Release Date: June 1999 Revision A1


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