|Category||Logic => Buffers/Drivers|
|Description||11-output Configurable Clock Buffer|
|Datasheet||Download GA1087 datasheet
Wide frequency range: 24 MHz to 105 MHz Output configurations: five outputs at fREF five outputs at fREF /2 or six outputs at 2x fREF four outputs at fREF Low output-to-output skew: 150 ps (max) within a groupMUX Divide Logic or ÷6 Output Buffers Group B Group A
TriQuint's is a configurable clock buffer which generates 11 outputs, operating over a wide range of frequencies from 24 MHz to 105 MHz. The outputs are available at either 1x and at 1x and 1/2 x the reference clock frequency, fREF. When one of the Group A outputs (Q5Q10) is used as feedback to the PLL, all Group A outputs will be at fREF , and all Group B outputs (Q0Q4) will 1/2 x fREF. When one of the Group B outputs is used as feedback to the PLL, all Group A outputs will at 2x fREF and all Group B outputs will be at fREF. A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation. Completely self-contained, this PLL requires no external capacitors or resistors. The PLL's voltage-controlled oscillator (VCO) has a frequency range from 280 MHz to 420 MHz. By feeding back one of the output clocks to FBIN, the PLL continuously maintains frequency and phase synchronization between the reference clock (REFCLK) and each of the outputs. TriQuint's patented output buffer design delivers a very low output-tooutput skew 150 ps (max). The GA1087's symmetrical TTL outputs are capable of sourcing and sinking 30 mA.
Near-zero propagation delay: +500 ps (max) +700 ps (max) TTL-compatible with 30 mA output drive 28-pin J-lead surface-mount packageFor additional information and latest specifications, see our website: www.triquint.com
The core of the is a Phase-Locked Loop (PLL) that continuously compares the reference clock (REFCLK) to the feedback clock (FBIN), maintaining a zero frequency difference between the two. Since one of the outputs (Q0Q8) is always connected to FBIN, the PLL keeps the propagation delay between the outputs and the reference clock within +500 ps for the GA1087-MC500, and within +700 ps for the GA1087-MC700. The internal voltage-controlled oscillator (VCO) has an operating range of 280 MHz to 420 MHz. The combination of the VCO and the Divide Logic enables the GA1087 to operate between 24 MHz and 105 MHz. The device features six divide modes: and ÷12. The Frequency Select pins, F0 and F1,
and the output used as feedback to FBIN set the divide mode as shown in Table 1. In the test mode, the PLL is bypassed and REFCLK is connected directly to the Divide Logic block via the MUX, as shown in Figure 1. This mode is useful for debug and test purposes. The various test modes are outlined in Table 2. In the test mode, the frequency of the reference clock is divided or 6. The maximum rise and fall time at the output pins is 1.4 ns. All outputs of the GA1087 are TTL-compatible with 30 mA symmetric drive and a minimum 2.4 V. Power Up/Reset Synchronization After-power-up or reset, the PLL requires time before it achieves synchronization lock. The maximum time required for synchronization (TSYNC) is 500 ms.Table 1. Frequency Mode Selection Feedback: Any Group A Output Q10)
Notes: 1. This mode produces outputs with 40/60 duty cycle for Q10 only.
Multiple ground and power pins on the GA1087 reduce ground bounce. Good layout techniques, however, are necessary to guarantee proper operation and to meet the specifications across the full operating range. TriQuint recommends bypassing each of the VDD supply pins to the nearest ground pin, as close to the chip as possible. Figure 2 shows the recommended power layout for the GA1087. The bypass capacitors should be located on the same side of the board as the GA1087. The VDD traces connect to an inner-layer VDD plane. All of the ground pins (GND) are connected to a small ground plane on the surface beneath the chip. Multiple through holes connect this small surface plane to an inner-layer ground plane. The capacitors (C1C5) are 0.1 mF. TriQuint's test board uses X7R temperature-stable capacitors in 1206 SMD cases.Figure 2. Top Layer Layout of Power Pins (approx. 3.3x)
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