|Category||Semiconductors => Data Converters => Digital-to-Analog Converters (DACs) => High Speed DACs (>10MSPS)|
|Part family||THS5641A 8-Bit, 100-MSPS Digital-to-Analog Converter (DAC)|
|Description||8-Bit, 100-MSPS Digital-to-Analog Converter (DAC) 28-SOIC -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download THS5641AIDW datasheet
|Operating Temperature Range(C)||-40 to 85|
|Sample / Update Rate(MSPS)||100|
|Approx. Price (US$)||3.19 | 1ku|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Wideband Complementary Current Output DAC Single-Ended Interface
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps | Doc
|• Noise Analysis for High Speed Op Amps (Rev. A)
As system bandwidths have increased, an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not, however, particularly comfortable with the calculations required to predic | Doc
|TSW2200EVM: TSW2200 Low-Cost Portable Power Supply Evaluation Module|
Member of the Pin-Compatible CommsDAC Product Family 100 MSPS Update Rate 8-Bit Resolution Signal-to-Noise and Distortion Ratio (SINAD) at 5 MHz: 50 dB Integral Nonlinearity INL: 0.25 LSB Differential Nonlinearity DNL: 0.25 LSB 1 ns Setup/Hold Time Glitch Energy: 5 pV-s Settling Time 35 ns Differential Scalable Current Outputs: 20 mA On-Chip 1.2-V Reference 3-V and 5-V Single Supply Operation Straight Binary or Twos Complement Input Power Dissipation: 3.3 V, Sleep Mode: 3.3 V Package: 28-Pin SOIC and TSSOPSOIC (DW) OR TSSOP (PW) PACKAGE (TOP VIEW)
CLK DVDD DGND MODE AVDD IOUT1 IOUT2 AGND COMP1 BIASJ EXTIO EXTLO SLEEP
The an 8-bit resolution digital-to-analog converter (DAC) optimized for video applications and digital data transmission in wired and wireless communication systems. The 8-bit DAC is a member of the CommsDAC series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin compatible 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package and pinout. The THS5641A offers superior ac and dc performance while supporting update rates to 100 MSPS. The THS5641A operates from an analog and digital supply 5.5 V. Its inherent low power dissipation 100 mW ensures that the device is well suited for portable and low power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 17 mW, thereby optimizing the power consumption for system needs. The THS5641A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and 1.2 V temperature compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5641A supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CommsDAC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
The THS5641A provides a nominal full-scale differential output current 20 mA and >300 k output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying DAC. The THS5641A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range to 85°C.
C1 SLEEP EXTLO 1.2 V REF 1 nF EXTIO CEXT 2 k RBIAS DVDD D[7:0] Logic Control 50 RLOAD BIASJ I BIAS + Control AMP 0.1 µF AVDD
TERMINAL NAME AGND AVDD BIASJ CLK COMP2 D[7:0] DGND DVDD EXTIO NO. I/O DESCRIPTION Analog ground return for the internal analog circuitry Positive analog supply voltage 5.5 V) Full-scale output current bias External clock input. Input data latched on rising edge of the clock. Compensation and decoupling node, requires 0.1 µF capacitor to AVDD. Internal bias node, requires 0.1 µF decoupling capacitor to AGND. Data bits 0 through D7 is most significant data bit (MSB), D0 is least significant data bit (LSB). Digital ground return for the internal digital logic circuitry Positive digital supply voltage 5.5 V) Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal reference output when EXTLO = AGND, requires 0.1 µF decoupling capacitor to AGND when used as reference output Internal reference ground. Connect to AVDD to disable the internal reference source DAC current output. Full scale when all input bits are set 1 Complementary DAC current output. Full scale when all input bits are 0 Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See timing diagram. No connection Asynchronous hardware power down input. Active High. Internal pulldown. Requires µs to power down but ms to power up.absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, AVDD (see Note 6.5 V DVDD (see Note 6.5 V Voltage between AGND and DGND. 0.5 V Supply voltage range, AVDD to DVDD. 6.5 V CLK, SLEEP, MODE (see Note V to DVDD 0.3 V Digital input D7D0 (see Note V to DVDD IOUT1, IOUT2 (see Note V to AVDD COMP1, COMP2 (see Note V to AVDD 0.3 V EXTIO, BIASJ (see Note V to AVDD 0.3 V EXTLO (see Note 0.3 V Peak input current (any input). 20 mA Peak total input current (all inputs). 30 mA Operating free-air temperature range, TA: to 85°C Storage temperature range. to 150°C Lead temperature mm (1/16 inch) from the case for 10 seconds. 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Measured with respect to AGND. 2. Measured with respect to DGND.
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