Details, datasheet, quote on part number: THS4505
PartTHS4505
CategorySemiconductors => Amplifiers => Operational Amplifiers (Op Amps) => High-Speed Op Amps (>=50MHz)
Part familyTHS4505 Wideband, Low-Distortion Fully Differential Amplifier
DescriptionWideband, Low-Distortion Fully Differential Amplifier 8-SOIC -40 to 85
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSY
SampleYes
DatasheetDownload THS4505 datasheet
Cross ref.Similar parts: MAX4444, AD8131AR, AD8131AR-REEL, AD8131AR-REEL7, AD8131ARM, AD8131ARM-REEL, AD8131ARM-REEL7, AD8131ARMZ, AD8131ARMZ-REEL, AD8131ARMZ-REEL7
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Specifications 
@ MHz8
Vn at 1kHz(Typ)(nV/rtHz)21
RatingCatalog
FeaturesN/A
Operating Temperature Range(C)-40 to 85
Rail-to-RailIn to V-
ArchitectureFully Differential
Total Supply Voltage(Min)(+5V=5, +/-5V=10)4.5
Input Bias Current(Max)(pA)4600000
Offset Drift(Typ)(uV/C)10
Acl, min spec gain(V/V)1
BW @ Acl(MHz)260
Package GroupMSOP-PowerPAD,SOIC,VSSOP
Total Supply Voltage(Max)(+5V=5, +/-5V=10)15
Approx. Price (US$)1.90 | 1ku
2nd Harmonic(dBc)79
3rd Harmonic(dBc)93
CMRR(Min)(dB)74
Output Current(Typ)(mA)130
Number of Channels(#)1
GBW(Typ)(MHz)210
Iq per channel(Typ)(mA)16
Iq per channel(Max)(mA)20
Vn at Flatband(Typ)(nV/rtHz)8
CMRR(Typ)(dB)80
Vos (Offset Voltage @ 25C)(Max)(mV)7
Slew Rate(Typ)(V/us)1800
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
8DSOICR-PDSO-G75TUBE4505 3.914.91.581.27
Application notes
• Noise Analysis for High Speed Op Amps (Rev. A)
As system bandwidths have increased, an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not, however, particularly comfortable with the calculations required to predic | Doc
Evaluation Kits
THS7530EVM: THS7530 Evaluation Module
THS4505EVM: THS4505 Evaluation Module
Spice Model
THS4505 PSpice Model (Rev. B) - ZIP (10/12/2011)
THS4505 TINA-TI Spice Model (Rev. B) - ZIP (10/12/2011)

 

Features, Applications

FEATURES

Fully Differential Architecture Bandwidth: 260 MHz Slew Rate: 1800 V/s IMD3: -73 dBc at 30 MHz OIP3: 29 dBm at 30 MHz Output Common-Mode Control Wide Power Supply Voltage Range: 15 V Input Common-Mode Range Shifted to Include the Negative Power Supply Rail Power-Down Capability (THS4504) Evaluation Module Available

APPLICATIONS

High Linearity Analog-to-Digital Converter Preamplifier Wireless Communication Receiver Chains Single-Ended to Differential Conversion Differential Line Driver Active Filtering of Differential Signals

DESCRIPTION

The THS4504 and THS4505 are high-performance fully differential amplifiers from Texas Instruments. The THS4504, featuring power-down capability, and the THS4505, without power-down capability, set new performance standards for fully differential amplifiers with unsurpassed linearity, supporting 12-bit operation through 40 MHz. Package options include the 8-pin SOIC and the 8-pin MSOP with PowerPADTM for a smaller footprint, enhanced ac performance, and improved thermal dissipation capability.

DESCRIPTION 260 MHz, 1800 V/s, VICR Includes VS370 MHz, 2800 V/s, VICR Includes VS370 MHz, 2800 V/s, Centered VICR V, 100 MHz, 43 V/s, 3.7 nVHz V, 150 MHz, 51 V/s, 1.3 nVHz V, 160 MHz, 450 V/s, 6.5 nVHz V, 150 MHz, 650 V/s, 7.6 nVHz

Even numbered devices feature power-down capability

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

over operating free-air temperature range unless otherwise noted (1)

UNIT Supply voltage, VS Input voltage, VI Output current, IO Differential input voltage, VID Continuous power dissipation Maximum junction temperature, TJ Maximum junction temperature, continuous operation, long-term reliability, TJ Storage temperature range, Tstg Lead temperature mm (1/16 inch) from case for 10 seconds (1) (2)

The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.

PACKAGE D (8 pin) DGN (8 pin) DGK (8 pin) (2) JC (C/W) 4.7 54.2 JA(C/W) POWER RATING 154 mW

This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long term reliability.

MIN NOM MAX Supply voltage Operating free-air temperature, TA Dual supply Single supply UNIT V C

PACKAGED DEVICES Power-down THS4504DGN THS4504DGNR Non-power-down MSOP-8-PP (1) ATA BDC Rails, 75 Tape and Reel, 2500 Rails, 100 Tape and Reel, 2500 Rails, 80 Tape and Reel, MSOP-8-PP (1) ASZ BDB Rails, 75 Tape and Reel, 2500 Rails, 100 Tape and Reel, 2500 Rails, 80 Tape and Reel, 2500 PACKAGE TYPE PACKAGE MARKINGS TRANSPORT MEDIA, QUANTITY

The PowerPAD is electrically isolated from all other pins.

Note A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin.


 

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