Details, datasheet, quote on part number: THS4502CDGN
PartTHS4502CDGN
CategorySemiconductors => Amplifiers => Operational Amplifiers (Op Amps) => High-Speed Op Amps (>=50MHz)
Part familyTHS4502 High-Speed Fully-Differential Amplifiers
TitleFully Differential
DescriptionHigh-Speed Fully-Differential Amplifiers 8-MSOP-PowerPAD 0 to 70
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSY
SampleNo
DatasheetDownload THS4502CDGN datasheet
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Specifications 
@ MHz8
FeaturesShutdown
Slew Rate(Typ)(V/us)2800
RatingCatalog
GBW(Typ)(MHz)300
Vos (Offset Voltage @ 25C)(Max)(mV)4
Approx. Price (US$)4.36 | 1ku
Vn at Flatband(Typ)(nV/rtHz)6.8
BW @ Acl(MHz)370
ArchitectureFully Differential
Output Current(Typ)(mA)120
3rd Harmonic(dBc)97
Total Supply Voltage(Min)(+5V=5, +/-5V=10)4.5
Input Bias Current(Max)(pA)4600000
Offset Drift(Typ)(uV/C)10
Acl, min spec gain(V/V)1
Vn at 1kHz(Typ)(nV/rtHz)27
Package GroupMSOP-PowerPAD,SOIC,VSSOP
Total Supply Voltage(Max)(+5V=5, +/-5V=10)15
2nd Harmonic(dBc)83
CMRR(Min)(dB)74
Operating Temperature Range(C)-40 to 85,0 to 70
Number of Channels(#)1
Iq per channel(Max)(mA)28
CMRR(Typ)(dB)80
Iq per channel(Typ)(mA)23
Rail-to-RailNo
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
8DGNHVSSOPS-PDSO-G80TUBEBCG 331.02.65
Application notes
• Analysis of fully differential amplifiers | Doc
• Fully differential amplifiers applications:Line termination,driving high-speed.. | Doc
• Noise Analysis for High Speed Op Amps (Rev. A)
As system bandwidths have increased, an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not, however, particularly comfortable with the calculations required to predic | Doc
Evaluation Kits
THS7530EVM: THS7530 Evaluation Module
THS4502EVM: THS4502EVM Evaluation Module
Spice Model
THS4503 PSpice Model (Rev. A) - ZIP (10/04/2011)

 

Features, Applications

FEATURES

Fully Differential Architecture Bandwidth: 370 MHz Slew Rate: 2800 V/s IMD3: -95 dBc at 30 MHz OIP3: 51 dBm at 30 MHz Output Common-Mode Control Wide Power Supply Voltage Range: 15 V

APPLICATIONS D High Linearity Analog-to-Digital Converter D Differential Line Driver D Active Filtering of Differential Signals

Preamplifier Wireless Communication Receiver Chains Single-Ended to Differential Conversion

D Centered Input Common-Mode Range D Power-Down Capability (THS4502) D Evaluation Module Available DESCRIPTION

The THS4502 and THS4503 are high-performance fully differential amplifiers from Texas Instruments. The THS4502, featuring power-down capability, and the THS4503, without power-down capability, set new performance standards for fully differential amplifiers with unsurpassed linearity, supporting 14-bit operation through 40 MHz. Package options include the 8-pin SOIC and the 8-pin MSOP with PowerPAD for a smaller footprint, enhanced ac performance, and improved thermal dissipation capability.

THS4140/1 THS4150/1 DESCRIPTION 370 MHz, 2800 V/s, VICR Includes VS- 370 MHz, 2800 V/s, Centered VICR V, 100 MHz, 43 V/s, 3.7 nVHz V, 150 MHz, 51 V/s, 1.3 nVHz V, 160 MHz, 450 V/s, 6.5 nVHz V, 150 MHz, 650 V/s, 7.6 nVHz

(1) Even numbered devices feature power-down capability

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

over operating free-air temperature range unless otherwise noted(1) UNIT

Supply voltage, VS Input voltage, VI Output current, IO (2) Differential input voltage, VID Continuous power dissipation Maximum junction temperature, TJ Operating free-air temperature range, TA: C suffix I suffix Storage temperature range, Tstg

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE D (8 pin) DGN (8 pin) JC (C/W) 4.7 JA(1) (C/W) 167 58.4 POWER RATING 1.11 W
Lead temperature mm (1/16 inch) from case for 10 seconds

MIN Dual supply Supply voltage Operating freeair temperature, TA Single supply C suffix I suffix 0 -40 NOM 5 5 MAX C UNIT V

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The THS450x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.

ORDERABLE PACKAGE AND NUMBER TEMPERATURE PLASTIC SMALL OUTLINE(1) (D) THS4502ID THS4503ID PLASTIC MSOP (DGN) THS4502IDGN THS4503IDGN PACKAGE MARKING BCG BCK BCI BCL

(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS4502IDR).

= +1, Single-ended input unless otherwise noted. THS4502 AND THS4503 PARAMETER TEST CONDITIONS TYP 25C AC PERFORMANCE = +1, PIN= -20 dBm, = 392 Small-signal bandwidth = +2, PIN= -30 dBm, Rf +5, PIN= -30 dBm, = +10, PIN = -30 dBm, 1.3 k Gain-bandwidth product Bandwidth for 0.1dB flatness Large-signal bandwidth Slew rate Rise time Fall time Settling time 0.01% 0.1% Harmonic distortion 2nd harmonic 3rd harmonic Third-order intermodulation distortion Third-order output intercept point Input voltage noise Input current noise Overdrive recovery time DC PERFORMANCE Open-loop voltage gain Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift INPUT Common-mode input range Common-mode rejection ratio Input impedance OUTPUT Differential output voltage swing Differential output current drive Output balance error Closed-loop output impedance (single-ended) = 20 PIN = -20 dBm, = 100 kHz = 1 MHz mA dB Min Typ dB pF Min Typ dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ > +10 PIN = -20 dBm VP VPP Step 2 VPP Step 2 VPP Step = 4 VPP = 4 VPP = 2 VPP = 8 MHz = 30 MHz = 8 MHz = 30 MHz = 30 MHz, Rf kHz tone spacing = 30 MHz, 392 , Referenced > 1 MHz > 100 kHz Overdrive 5.5 V dBc dBm nV/Hz pA/Hz ns MHz V/s ns Typ 25C OVER TEMPERATURE to 85C UNITS MIN/ TYP/ MAX


 

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