|Category||Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => Transceivers|
|Description||ti SLK2721, OC-48/24/12/3 Sonet SDH Multi-rate Transceiver With Enhanced Jitter Tolerance|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SLK2721IPZP datasheet
|SLK2721 OC-48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER WITH ENHANCED JITTER TOLERANCE
Support Clock/Data Recovery and Multiplexer/Demultiplexer Functions Enhanced Jitter Tolerance Over SLK2701 Supports 2.7 Gbps OC-48 FEC Rate, OC-24, OC-12, Gigabit Ethernet, and OC-3 Data Rate With Autorate Detection Supports Transmit Only, Receiver Only, Transceiver and Repeater Functions in a Single Chip Through Configuration Pins Supports SONET/SDH Frame Detection On-Chip PRBS Generation and Verification Supports 4-Bit LVDS (OIF99.102) Electrical Interface Single 2.5-V Power Supply Interfaces to Back Plane, Copper Cables, or Optical Modules Hot Plug Protection
Serial Interface With Programmable De-Emphasis for the Serial Output On-Chip Termination for LVDS and PECL-Compatible Interface Receiver Differential Input Thresholds 150 mV Minimum Supports SONET Loop Timing Low Power at OC-48 Data Rate ESD Protection kV 622-MHz Reference Clock Maintains Clock Output in Absence of Data Local and Remote Loopback Parity Checking and Generation for the LVDS Interface 100-Pin PZP Package With PowerPad Designdescription
The SLK2721 device is a single chip, multirate transceiver that derives high-speed timing signals for SONET/ SDH-based equipment. The device performs clock and data recovery, serial-to-parallel/parallel-to-serial conversion, and a frame detection function conforming to the SONET/SDH standards. The device can be configured to operate under or OC-3 data rate through the rate selection pins or the autorate detection function. An external reference clock operating at 622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions. The SLK2721 device accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at the or OC-48 data rate. It also recovers the data and clock from the serial SONET stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL-compatible differential interface. The SLK2721 device supports an FEC data rate to 2.7 Gbps when configured to operate at the OC-48 data rate and provided with an external reference clock that is properly scaled. The SLK2721 device provides a comprehensive suite of built-in tests for self-test purposes including local and remote loopback and pseudorandom bit stream (PRBS) (27-1) generation and verification. The device comes a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on the control pins. The SLK2721 device is very power efficient, dissipating less than at 2.488 Gbps, the OC-48 data rate. It is characterised for operation from to 85°C.AVAILABLE OPTIONS PACKAGE to 85°C PowerPAD QUAD (PZP) SLK2721PZP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TXDATA0..TXDATA3 TXCLKP TXCLKN TXPARP TXPARN PAR_VALID RLOOP TXCLKRCP TXCLKRCN REFCLKP REFCLKN LCKREFN LOOPTIME RSEL(01) To All The Logic RESET LOL LLOOP PRBSPASSParity Generator RXPARP RXPARN RXCLKP TXCLKN FRAMEN FSYNCP FSYNCN
GNDLVDS TXPARP TXPARN VDDLVDS GNDLVDS REFCLKN REFCLKP GNDLVDS VDDLVDS GNDLVDS TXDATA3P TXDATA3N TXCLKN TXCLKP VDDLVDS GNDLVDS
GND PAR_VALID VDD PRE1 PRE2 GND VDDA STXDON STXDOP GNDA VDDPLL GNDPLL GNDA SRXDIP SRXDIN VDDA CONFIG0 CONFIG1 GND SIGDET PS VDD GND LCKREFN VDD
VDDLVDS FSYNCN FSYNCP VDDLVDS TXCLKSRCN TXCLKSRCP GNDLVDS RXCLKN RXCLKP RXDATA1P RXDATA1N VDDLVDS GNDLVDS RXDATA3P RXDATA3N RXPARP RXPARN RLOOP LLOOP RSVD LOOPTIME
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