|Category||Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => Transceivers|
|Description||ti SLK2511, OC-48,24,12 Sonet SDH Multi-rate Transceiver|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SLK2511IPZP datasheet
Support Clock/Data Recovery and Multiplexer/Demultiplexer Functions Supports OC-24, OC-12, Gigabit Ethernet, and OC-3 Data Rate With Autorate Detection Supports Transmit Only, Receiver Only, Transceiver and Repeater Functions in a Single Chip Through Configuration Pins Supports SONET/SDH Frame Detection On-Chip PRBS Generation and Verification Supports 4-Bit LVDS (OIF99.102) Electrical Interface Parity Checking and Generation for the LVDS Interface Single 2.5-V Power Supply Interfaces to Back Plane, Copper Cables, or Optical ModulesD Hot Plug Protection D Low Jitter PECL Compatible Differential
Serial Interface With Programmable De-Emphasis for the Serial Output On-Chip Termination for LVDS and PECL Compatible Interface Receiver Differential Input Thresholds 150 mV Min Supports SONET Loop Timing Low Power CMOS ESD Protection or 622-MHz Reference Clock Maintains Clock Output in Absence of Data Local and Remote Loopback 100-Pin PZP Package With PowerPad Design With 5x5 mm (Typ) Heatsinkdescription
The is a single chip multirate transceiver IC used to derive high-speed timing signals for SONET/SDH based equipment. The chip performs clock and data recovery, serial-to-parallel/parallel-to-serial conversion and frame detection function conforming to the SONET/SDH standards. The device can be configured to operate under or OC-3 data rates through the rate selection pins or the autorate detection function. An external reference clock operating at 155.52 MHz or 622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions. The SLK2511 accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal or OC-48 rates. It also recovers the data and clock from the serial SONET stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL compatible differential interface. The SLK2511 provides a comprehensive suite of built-in tests for self-test purposes including local and remote loopback and PRBS (27-1) generation and verification. The device comes a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on the control pins. The SLK2511 is power efficient, dissipating less than at 2.488 Gbps, the OC-48 data rate, and it is characterised for operation from to 85°C.AVAILABLE OPTIONS PACKAGE to 85°C PowerPAD QUAD (PZP) SLK2511IPZP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TXDATA0..TXDATA3 TXCLKP TXCLKN TXPARP TXPARN PAR_VALID RLOOP TXCLKSRCP TXCLKSRCN REFCLKP REFCLKN REFCLKSEL LCKREFN LOOPTIME RSEL(01) To All The Logic RESET LOL LLOOP PRBSPASSParity Generator RXPARP RXPARN RXCLKP RXCLKN FRAMEN FSYNCP FSYNCN
GNDLVDS TXPARP TXPARN VDDLVDS GNDLVDS REFCLKN REFCLKP GNDLVDS VDDLVDS GNDLVDS TXDATA3P TXDATA3N TXCLKN TXCLKP VDDLVDS GNDLVDS
GND PAR_VALID VDD PRE1 PRE2 GND VDDA STXDON STXDOP GNDA VDDPLL GNDPLL GNDA SRXDIP SRXDIN VDDA CONFIG0 CONFIG1 GND SIGDET PS VDD GND LCKREFN VDD
VDDLVDS FSYNCN FSYNCP VDDLVDS TXCLKSRCN TXCLKSRCP GNDLVDS RXCLKN RXCLKP RXDATA1P RXDATA1N VDDLVDS GNDLVDS RXDATA3P RXDATA3N RXPARP RXPARN RLOOP LLOOP RSVD LOOPTIMEGND FRAME_EN GND VDD GND VDD GND AUTO_DETECT VDD RSEL1 RSEL0 REFCLKSEL PRBSEN PRBSPASS TESTEN
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