|Category||Power Management => Battery Management => Battery Protection|
|Description||ti BQ2058T, 2-Cell Lithium-ion Pack Supervisor ic|
|Company||Texas Instruments, Inc.|
|Datasheet||Download BQ2058TRSN-C2 datasheet
® Protects and individually monitors two Li-Ion series cells for overvoltage, undervoltage ® Monitors pack for overcurrent ® Designed for battery pack integration ® Minimal external components ® Drives external FET switches ® Selectable overvoltage OV ) thresholds
The bq2058T Lithium Ion Pack Supervisor is designed to control the charge and discharge cell voltage limits for two lithium-ion (Li-Ion) series cells, accommodating battery packs containing series/parallel configurations. The low operating current does not overdischarge the cells during periods of storage and does not significantly increase the system discharge load. The bq2058T can be part of a low-cost Li-Ion charge control system within the battery pack. The bq2058T controls two external FETs to limit the charge and discharge potentials. The bq2058T allows charging when each individual cell voltage is below VOV (overvoltage limit). If the voltage on any cell exceeds VOV for a user-configurable delay period (tOVD), the open-drain CHG pin goes to the high-impedance state, shutting off
charge to the battery pack. This safety feature prevents overcharge of any cell within the battery pack. After an overvoltage condition occurs, each cell must fall below VCE (charge enable voltage) for the bq2058T to re-enable charging. The bq2058T protects batteries from overdischarge. If the voltage on any cell falls below VUV (undervoltage limit) for a user-configurable delay period (tUVD), the DSG output is driven low, shutting off the battery discharge. This safety feature prevents overdischarge of any cell within the battery pack. The bq2058T also stops discharge on detection of an overcurrent condition, such as a short circuit. If an overcurrent condition occurs for a userconfigurable delay period (tOCD), the DSG output is driven low, disconnecting the load from the pack. DSG remains low until removal of the short circuit or overcurrent condition.® Supply current: 12µA typical ® Sleep current: 0.7µA typical 16-pin 150-mil narrow SOIC
CHG Charge control output Pack disable input Low potential input Overcurrent sense low-side input Battery 2 negative input Battery 1 negative input BAT1P DSG UVD OVD OCD VCC CSH Discharge control output Undervoltage delay input Overvoltage delay input Overcurrent delay input High potential input Overcurrent sense high-side input Battery 1 positive input
CHG Charge control output This open-drain output controls the charge path to the battery pack. Charging is allowed when high. CTL Pack disable input When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal operation, the CTL pin is low. VSS CSL Low potential input CSH Overcurrent sense low-side input This input is connected between the low-side discharge FET (or sense resistor) and BAT2N to enable overcurrent sensing in the battery pack's ground path. BAT1P BAT2N Battery 2 negative inputs (3 pins) These pins are connected to the negative terminal of the cell designated BAT2 in Figure 2. BAT1N Battery 1 negative input This input is connected to the negative terminal of the cell designated BAT1 in Figure 2. DSG Discharge control output This push-pull output controls the discharge path to the battery pack. Discharge is allowed when high. Overcurrent sense high-side input n e cte e n the high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack's positive supply path. Battery 1 positive input This input is connected to the positive terminal of the cell designated BAT1 in Figure 2. OCD OVD UVD Undervoltage delay input This input uses an external capacitor to VCC to set the undervoltage delay timing. Overvoltage delay input This input uses an external capacitor to VCC to set the overvoltage delay timing. Overcurrent delay input This input uses an external capacitor to VCC to set the overcurrent delay timing. VCC High potential inputs (2 pins)Over_charge Pin 1 QB CHG Charge Control Output (open drain)
Capacitor Pin 13 OVD Discharge Off Delay Capacitor Input All_Below_VCE
Sleep D CK Pin 16 QB Reset Discharge Control Output (totem pole) DSG
Non-Retrigger Oneshot Reset Capacitor UVD Pin 14 Charge Off Delay Capacitor Input Pin 10 CSH Pin 9 Pin 4 Pin 7
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