|Category||Power Management => Battery Management => Battery Protection|
|Description||ti BQ2058, 3-, 4-Cell Lithium-ion Pack Supervisor ic|
|Company||Texas Instruments, Inc.|
|Datasheet||Download BQ2058CSN-C5 datasheet
® Protects and individually monitors three or four Li-Ion series cells for overvoltage, undervoltage ® Monitors pack for overcurrent ® Designed for battery pack integration ® Minimal external components ® Drives external FET switches ® Selectable overvoltage (VOV ) thresholds
The bq2058 Lithium Ion Pack Supervisor is designed to control the charge and discharge cell voltages for three or four lithium ion (Li-Ion) series cells, accommodating battery packs containing series/parallel configurations. The low operating current does not overdischarge the cells during periods of storage and does not significantly increase the system discharge load. The bq2058 can be part of a low-cost Li-Ion charge control system within the battery pack. The bq2058 controls two external FETs to limit the charge and discharge potentials. The bq2058 allows charging when each individual cell voltage is below VOV (overvoltage limit). If the voltage on any cell exceeds VOV for a user-configurable CHG pin is delay period (tOVD), the driven high, shutting off charge to the battery pack. This safety feature pre-
vents overcharge of any cell within the battery pack. After an overvoltage condition occurs, each cell must fall below VCE (charge enable voltage) for the bq2058 to re-enable charging. The bq2058 protects batteries from overdischarge. If the voltage on any cell falls below VUV (undervoltage limit) for a user-configurable delay period (tUVD), the DSG output is driven high, shutting off the battery discharge. This safety feature prevents overdischarge of any cell within the battery pack. The bq2058 also stops discharge on detection of an overcurrent condition, such as a short circuit. If an overcurrent condition occurs for a userconfigurable delay period (tOCD), the DSG output is driven high, disconnecting the load from the pack. DSG remains high until removal of the short circuit or overcurrent condition.® Supply current: 25µAtypical ® Sleep current: 16-pin 150-mil narrow SOIC
CHG Charge control output Pack disable input Low potential input Current sense low-side input Battery 4 negative input Battery 3 negative input Battery 2 negative input Battery 1 negative input BAT1P DSG NSEL UVD OVD OCD VCC CSH Discharge control output or 4-cell selection Undervoltage delay input Overvoltage delay input Overcurrent delay input High potential input Current sense high-side input Battery 1 positive input
CHG Charge control output This push-pull output controls the charge path to the battery pack. Charging is allowed when low. CTL Pack disable input When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal operation, the CTL pin is low. VSS CSL Low potential input Overcurrent sense low-side input This input is connected between the low-side discharge FET (or sense resistor) and BAT4N to enable overcurrent sensing in the battery pack's ground path. BAT4N Battery 4 negative input This input is connected to the negative terminal of the cell designated BAT4 in Figure 2. BAT3N Battery 3 negative input This input is connected to the negative terminal of the cell designated BAT3 in Figure 2. BAT2N Battery 2 negative input This input is connected to the negative terminal of the cell designated BAT2 in Figure 2. BAT1N Battery 1 negative input This input is connected to the negative terminal of the cell designated BAT1 in Figure 2. BAT1P VCC CSH OVD UVD NSEL DSG This input is connected in a threecell configuration. Discharge control output This push-pull output controls the discharge path to the battery pack. Discharge is allowed when low. Number of cells input This input selects the number of series cells in the pack. NSEL should connect to VCC for four cells and to VSS for three cells. Undervoltage delay input This input uses an external capacitor to VCC to set the undervoltage delay timing. Overvoltage delay input This input uses an external capacitor to VCC to set the overvoltage delay timing. OCD Overcurrent delay input This input uses an external capacitor to VCC to set the overcurrent delay timing. High potential input Overcurrent sense high-side input This input is connected between h e high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack's positive supply path. Battery 1 positive input This input is connected to the positive terminal of the cell designated BAT1 in Figure 2.
Number of Cells Configuration Pins BAT1N tied to BAT1P NSEL = VSS Battery Pins BAT1N Positive terminal of first cell 3 cells BAT2N Negative terminal of first cell BAT3N Negative terminal of second cell BAT4N Negative terminal of third cell BAT1P Positive terminal of first cell BAT1N Negative terminal of first cell 4 cells NSEL = VCC BAT2N Negative terminal of second cell BAT3N Negative terminal of third cell BAT4N Negative terminal of fourth cell
Pin 9 B1P Pin 8 B1N Number of Cells Select + Clock Pin 7 B2N Pin 6 B3N Pin 5 B4N Sleep Pin 15 NSEL Sel2 Sel1Any_Below_VUV D CK Edge Out QB Reset Non-Retrigger Oneshot Reset UVD
Charge Off Delay Capacitor Input Sense High-side Input
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