Details, datasheet, quote on part number: TDA758013TR
PartTDA758013TR
Category
DescriptionFm/am Digital if Sampling Processor
CompanyST Microelectronics, Inc.
DatasheetDownload TDA758013TR datasheet
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Features, Applications

FEATURES

FM/AM IF SAMPLING DSP ON-CHIP ANALOGUE TO DIGITAL CONVERTER FOR 10.7MHz IF SIGNAL CONVERSION FM CHANNEL EQUALIZATION FM ADJACENT CHANNEL SUPPRESSION RECEPTION ENHANCEMENT IN MULTIPATH CONDITION STEREO DECODER AND WEAK SIGNAL PROCESSING 2 CHANNELS SERIAL AUDIO INTERFACE (SAI) WITH SAMPLE RATE CONVERTER I2C AND BUFFER-SPI CONTROL INTERFACES RDS FILTER, DEMODULATOR & DECODER INTER PROCESSOR TRANSPORT INTERFACE FOR ANTENNA AND TUNER DIVERSITY FRONT-END AGC FEEDBACK

DESCRIPTION

The is an integrated circuit implementing an advanced mixed analogue and digital solution to perform the signal processing of a AM/FM channel. The HW&SW architecture has been devised to perform a digital equalization of the FM/AM channel and a real rejection of adjacent channels and any other signals interfering with the listening of the desired station. In severe Multiple Paths conditions, the reception is improved to get high quality audio.

The algorithm is self-adaptive, thus it requires no "on-the-field" adjustments after the parameters optimization. The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a "tuner device" (it is highly recommended the TDA7515). The 24bit-DSP allows flexibility in the algorithms implementation, thus giving some freedom for customer required features. The total processing power offers a significant headroom for customer's software requirement, even when the channel equalization and the decoding software is running. The Program and Data Memory space can be loaded from an external non volatile memory via I2C or SPI. The oscillator module works with an external 74.1MHz quartz crystal. It has very low Electro Magnetic Interference, as it introduces very low distortion, and in any case harmonics fall outside the Radio bandwidth. The companion tuner device receives the reference clock through a differential ended interface, which works off the Oscillator module by properly dividing down the master clock frequency. That allows the overall system saving an additional crystal for the tuner. After the IF conversion, the digitized baseband signal passes through the Base Band processing section, either FM or AM, depending on the listener selection. The FM Base Band processing comprises of Stereo Decoder, Spike Detection and Noise Blanking. The AM Noise Blanking is fully software implemented. The internal RDS filter, demodulator and decoder features complete functions to have the output data available through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background and in parallel with other DSP processing. This mode (RDS-only) allows current consumption saving for low power application modes. An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the DSP task and frequently respond to the interrupt from the control interface. Serial Audio Interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully independent bidirectional data channels, with separate clocks allows the use TDA7580 as general purpose digital audio processor. A fully Asynchronous Sample Rate Converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate. An Inter Processor Transport Interface (HS3I, High Speed Synchronous Serial Interface) is also available for a modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is about a Synchronous Serial Interface which exchanges data up to the MPX rate. It has been designed to reduce the Electro Magnetic Interference toward the sensitive analogue signal from the Tuner. General Purpose I/O registers are connected to and controlled by the DSP, by means of memory map. A Debug and Test Interface is available for on-chip software debug as well as for internal registers read/write operation.

Symbol VDD VDD3 Power supplies (1) Parameter Nom. 1.8V Nom. 3.3V Value to 4.0 Unit V

Analog Input or Output Voltage belonging 3.3V IO ring (VDDSD, VDDOSC) Digital Input or Output Voltage, 5V tolerant Normal(2) Fail-safe(3) Nom. 1.8V Nom. 3.3V

All remaining Digital Input or Output Voltage Tj Tstg Operating Junction Temperature Range Storage Temperature

Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Note: 1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies (VDD, VMTR). 2. During Normal Mode operation VDD3 is always available as specified 3. During Fail-safe Mode operation VDD3 may be not available.

Symbol VDD VDDH VOSC VDDSD VMTR Parameter 1.8V Power Supply Voltage 3.3V Power Supply Voltage (1) 3.3V Power Supply Voltage (1) 3.3V Power Supply Voltage (1) 1.8V Power Supply Voltage Comment Core Power Supply IO Rings Power Supply (with GNDH) Oscillator Power Supply (GNDOSC) IF ADC Power Supply (with GNDSD) DAC-Keying and Tuner clock Power Supply (with GNDMTR ) Min. Typ. Max. Unit

Note: 1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD.
Symbol Rth j-amb Parameter Thermal resistance junction to ambient Value 68 Unit °C/W

 

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