Details, datasheet, quote on part number: TDA7551
PartTDA7551
CategoryMultimedia => Audio => Processors
DescriptionDigital Signal Processing ic For Speech And Audio Application
CompanyST Microelectronics, Inc.
DatasheetDownload TDA7551 datasheet
  

 

Features, Applications

DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND AUDIO APPLICATIONS

24-BIT, FIXED POINT, 45 MIPS DSP CORE LARGE ON-BOARD PROGRAM RAM AND DATA RAM (16Kw-24 BIT DATA RAM AND 16Kw-24 BIT PROGRAM RAM) INTEGRATED STEREO, 16-BIT SIGMADELTA A/D AND D/A CONVERTERS PROGRAMMABLE CODEC SAMPLE RATE FROM TO 48 kHz ON-BOARD PLL FOR CORE CLOCK AND CONVERTERS MANAGEMENT OF EXTERNAL FLASH / SRAM / DRAM MEMORY BANK I2C OR SPI SERIAL INTERFACE FOR EXTERNAL CONTROL 80-PIN TQFP, 0.65 mm PITCH AUTOMOTIVE GRADE (FROM to +85C) DESCRIPTION The is a high performances, fully programmable 24-bit, 45 MIPS Digital Signal Processor (DSP), designed to support several speech and audio applications, as Automatic Speech BLOCK DIAGRAM

Recognition, Speech Synthesis, Speaker Verification, Echo and Noise Cancellation. Software for these applications is licenced by Lernout & Hauspie and BIT Innovation Technologies. It offers an effective solution for this kind of applications because of the A/D and D/A converters and the big amount of memory integrated on chip. APPLICATIONS Real time digital speech and audio processing: speech recognition, speech synthesis, speech compression, echo canceling, noise canceling, speaker verification.

Symbol Vdd Parameter 3.3V Power Supply Voltage Input or Output Voltage Input or Output Voltage (Note 1)

Note 1: For 5V tolerant inputs and 5V tolerant output buffers in tri-state mode.
Symbol Rth j-pins Parameter Thermal Resistance Junction pins Max. Value 55 Unit C/W

GND TEST3 SCK LRCK GND GPIO1 MOSI VDD SDI VDD SDO GPIO0 GPIO5 DBCK EMI_A21 DWRN TEST1 TEST2 MISO DBIN

CGNDA VINL VINR CGND CVDD VOUTL VOUTR VDD GND GPIO6 GPIO2 GND VDD SDA/SS SCL/SCK INTN NRESET DBRQN DBOUT

N. Name EMI_AD5 EMI_AD6 VDD GND EMI_AD7 EMI_A8 Type I/O I I/O O Description EMI Multiplexed Address/Data Line 5. these pin acts as the EMI multiplexed address and data line 5. In DRAM mode acts as Address 1. EMI Multiplexed Address/Data Line 6. these pin acts as the EMI multiplexed address and data line 6. In DRAM mode acts as Address 2. Digital power supply Ground EMI Multiplexed Address/Data Line 7. these pin acts as the EMI multiplexed address and data line 7. In DRAM mode acts as Address 3. EMI Address Line 8. these pin acts as the EMI address line 8. The interface is designed to address to 4 Mbytes of External Flash, EPROM or SRAM. In DRAM mode acts as Address 4. EMI Address Line 9. these pin acts as the EMI address line 9. In DRAM mode acts as Address 5. EMI Address Line 10. these pin acts as the EMI address line 10. In DRAM mode acts as Address 6. EMI Address Line 11. these pin acts as the EMI address line 11. In DRAM mode acts as Address 7. EMI Address Line 12. these pin acts as the EMI address line 12. In DRAM mode acts as Address 8. EMI Address Line 13. these pin acts as the EMI address line 13. In DRAM mode acts as Address 9. EMI Address Line 14. these pin acts as the EMI address line 14. In DRAM mode acts as Address 10. EMI Address Line 15. these pin acts as the EMI address line 15. In DRAM mode acts as Address 11. Digital power supply Ground EMI Address Line 16. these pin acts as the EMI address line 16. In DRAM mode acts as Address 12. EMI Address Line 17. these pin acts as the EMI address line 17. EMI Address Line 18. these pin acts as the EMI address line 18. EMI Address Line 19. these pin acts as the EMI address line 19. EMI Address Line 20. these pin acts as the EMI address line 20. EMI Address Line 21. these pin acts as the EMI address line 21. In DRAM mode acts as Row address Strobe. EMI Write Enable. This pin serves as the write enable for the EMI Test 1. Used for test: set to LOW for normal operation Test 2. Used for test: set to HIGH for normal operation SPI Master Input Slave Output Serial Data. Serial Data Input for SPI type serial Port when in SPI master Mode and Serial Data Output when in SPI Slave Mode SPI Master Output Slave Input Serial Data. Serial Data Output for SPI type serial Port when in SPI master Mode and Serial Data Input when in SPI Slave Mode Digital Power Supply Ground Test 3. Used for test: set to LOW for normal operation SAI Data Input SAI Bit Clock SAI Left/Right Clock


 

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