|Description||Digital AM/FM Signal Processor|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download TDA7500A datasheet
FULL SOFTWARE FLEXIBILITY WITH TWO 24X24 BIT DSP CORES SOFTWARE AM/FM, AUDIO AND SOUNDPROCESSING HARDWARE RDS FILTER, DEMODULATOR & DECODER INTEGRATED CODEC (4ADCs, 6DACs) IIC AND SPI CONTROL INTERFACES SPI DEDICATED TO DISPLAY MICRO 6 CHANNEL SERIAL AUDIO INTERFACE (SAI) SPDIF RECEIVER WITH SAMPLE RATE CONVERTER EXTERNAL MEMORY INTERFACE (EMI) DOUBLE DEBUG INTERFACE ON-CHIP PLL 5V-TOLERANT 3V I/O INTERFACE 12x2 MULTIFUNCTION GENERAL PURPOSE I/O PORTS
DESCRIPTION The is an integrated circuit implementing a fully digital, integrated and advanced solution to perform the signal processing in front of the power amplifier and behind the AM/FM tuner or any other audio source. The chip integrates two 45 MIPs DSP cores: one for stereo decoding, noise blanking, weak signal processing and multipath detection and one for sound processing, Dolby B, echo and noise cancelling for the telephone.ADCVDD ADCGND AVDD AGND CLK in Crystal Oscillator
Oversampl. Filter Grp & blk sync., error correction IIC / SPI 1 SPI 2 SAI Transmitter External Memory InterfaceError corr. RDS blocks or RDS clk, dat, qual
4 10 word SPI 1 receive stack 2ch Sample Rate Converter
X Ram 1024 Y Ram 1024 P Ram 5632 P Rom 512 Audio processing, Sound processing, Noise & Echo Canc.
DESCRIPTION (continued) An I2C/SPI interface is implemented for control and communication with the main micro. A separate SPI is available to interface the display micro.The DSP cores are integrated with their associated data and program memories. The peripherals and interfaces I 2C, SPI, Serial Audio Interface (SAI), PLL Oscillator, External Memory Interface, (EMI), General Purpose I/O register (Port A) and the D/A registers are connected to and controlled by DSP0, whereas the A/D registers, the SPDIF and the General Purpose I/O register (Port B) are connected to and controlled DSP1. An hardware RDS filter , demodulator and decoder block is also embedded. No support is needed from the DSPs but at initialisation so that RDS can work in background and in parallel with other DSP processing. Separated Debug and Test Interfaces are connected to both DSP cores. The TDA7500A is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also available. The flexibility allowed by the wide memory space and by the two powerfull DSP cores make the TDA7500A usable for different applications. In example, inside the main radio as an audio co-processor or to perform the signal processing and equalisation associated to a digital power amplifier. ABSOLUTE MAXIMUM RATINGSSymbol VDD VCC Vaio Vdio Vdi5 Tj Tstg Power supplies Parameter Digital Analog Value to 150 Unit °C
Analog Input and Output Voltage Digital Input and Output Voltage Digital Input Voltage (5V tolerant) Operating Junction Temperature Range Storage Temperature
Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Symbol Rth j-amb Parameter Thermal resistance junction to ambient (1) Thermal resistance junction to ambient (2) Rth j-case Thermal junction to case (3) Value 20 5 Unit °C/WNote: 1. In still air On 4 layers board with soldered slug 3. Measured on top side of the package
GND1 VDD1 TESTEN I Name Type Description Ground pin dedicated to the digital circuitry. Supply pin dedicated to the digital circuitry. Test Enable (Input). When low, puts the chip into test mode and muxes the XTI clock to all flip-flops. When TEST_SE is also active, the scan chain shifting is enabled. To be connected to Vdd in operating mode. SCAN Enable (Input). When high with TESTEN also active, controls the shifting of the internal scan chains. When active with TESTEN not active, sets all tri-state outputs into hi-impedance mode. To be connected to GND in operating mode. System Reset (Input). A low level applied to NRESET input initializes the IC. I2C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/ General Purpose I/O (Input/Output). Clock line for I2C bus. If SPI interface is enabled, behaves as SPI bit clock. Optionally it can be used as general purpose I/O controlled DSP0. I2C Serial Data Line (Input/Output)/SPI Master Input Slave Output Serial Data (Input/Output)/General Purpose I/O (Input/ Output). Data line for I2C bus. If SPI is enabled, behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Output Slave Input Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Slave Select (Input)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit clock. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Input Slave Output Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/ O controlled by DSP0. SPI Master Output Slave Input Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Slave Select (Input)/General Purpose I/O (Input/Output). Behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0.
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