Details, datasheet, quote on part number: STM1815YWX7F
PartSTM1815YWX7F
CategoryPower Management => Supervisory Circuits => System Supervisors/Reset
DescriptionLow Power Reset Circuit

AND 5V SUPPLY VOLTAGES
FOUR OUTPUT CONFIGURATIONS
C Push-Pull, Active-High (STM1812,1817)
C Push-Pull, Active-Low (STM1810,1815)
C Open Drain, Active-Low (STM1811,1816)
C Open Drain, Active-Low with Push-Button
Detect (STM1813,1818)
RESET PULSE WIDTH - 100ms (min)
LOW SUPPLY CURRENT - 4uA (typ)
GUARANTEED ASSERTION DOWN TO
VCC = 1.0V (0C to 105C)
FACTORY-TRIMMED RESET
THRESHOLDS OF 2.55V, 2.88V, 3.06V,
4.37V, and 4.62V (typ)
POWER SUPPLY TRANSIENT IMMUNITY
PUSH-BUTTON/MANUAL RESET DETECT
(STM1813/1818)
OPERATING TEMPERATURE:
C40C TO 105C
2.5% RESET THRESHOLD ACCURACY
(C40C TO 105C)
AVAILABLE IN THE SOT23-3 PACKAGE
FULLY COMPATIBLE WITH DS181x AND
MXD181x PRODUCTS
CompanyST Microelectronics, Inc.
DatasheetDownload STM1815YWX7F datasheet
  

 

Features, Applications

PRECISION MONITORING 3V, 3.3V, AND 5V SUPPLY VOLTAGES FOUR OUTPUT CONFIGURATIONS Push-Pull, Active-High (STM1812,1817) Push-Pull, Active-Low (STM1810,1815) Open Drain, Active-Low (STM1811,1816) Open Drain, Active-Low with Push-Button Detect (STM1813,1818) RESET PULSE WIDTH - 100ms (min) LOW SUPPLY CURRENT - 4uA (typ) GUARANTEED ASSERTION DOWN TO VCC to 105C) FACTORY-TRIMMED RESET THRESHOLDS 3.06V, 4.37V, and 4.62V (typ) POWER SUPPLY TRANSIENT IMMUNITY PUSH-BUTTON/MANUAL RESET DETECT (STM1813/1818) OPERATING TEMPERATURE: 105C 2.5% RESET THRESHOLD ACCURACY TO 105C) AVAILABLE IN THE SOT23-3 PACKAGE FULLY COMPATIBLE WITH DS181x AND MXD181x PRODUCTS

3.3V/ 3.0V Active-Low RESET (Push-Pull) (1) Active-Low RESET (Open Drain) Active-High RESET (Push-Pull) Active-Low RESET (Open Drain, Bi-directional, with MR Detect)

Note: 1. Active-low RST with internal pull-up resistor

FEATURES SUMMARY. 1 Figure 1. Packages. 1 Table 1. Device Options. 1 SUMMARY DESCRIPTION. 4 Figure 2. Table 2. Figure 3. Figure 4. Logic Diagram. Signal Names. SOT23-3 Connections. Hardware Hookup.........................4.....4.....4.....5

FUNCTIONAL BLOCK DIAGRAMS. 5 Figure 5. Push-pull Active-Low Output (STM1810/1812/1815/1817). 5 Figure 6. Open Drain, Active-Low Output (STM1811/1816). 5 Figure 7. Open Drain, Active-Low Output (Bi-directional, Manual Reset Detect, STM1813/1818). 5 PIN DESCRIPTIONS. 6 Table 3. Table 4. Table 5. Table STM1812/STM1817. STM1813/STM1818.............................................................................................................................................................6.....6.....6.....6

OPERATION. 7 Reset Output. 7 Push-Button Detect Reset (STM1813/1818). 7 Interfacing to Bidirectional Microcontrollers (MCU's). 7 Negative Going VCC Transients. 7 Valid RST Output Down to VCC 0V. 7 Figure 8. Reset Timing Diagram. 7 Figure 9. Push-Button Manual Reset with MR Detect (STM1813/1818). 8 Figure 10.Manual Reset Timing Diagram, Switch Bounce/Debounce (STM1813/1818). 8 Figure 11.Interfacing MCUs with Bi-Directional Reset Pins (RST, Open Drain, STM1811/1816). 8 Figure 12.Valid Reset (RST) Output Down to VCC = 0V (Push-pull). 9 Figure 13.Valid Reset (RST) Output Down to VCC = 0V (Push-pull). 9 TYPICAL OPERATING CHARACTERISTICS. 10 Figure 14.Supply Current vs. Temperature (no load). 10 Figure 15.Normalized Reset Time-out Period (trec) vs. Temperature - VOD = VTH VCC. 10 Figure 16.VCC-to-Reset Output Delay vs. Temperature - VOD = VTH VCC. 11 Figure 17.Voltage Output Low vs. ISINK. 11 Figure 18.Voltage Output High vs. ISOURCE. 12 Figure 19.Normalized Reset Threshold vs. Temperature. 12 Figure 20.Max Transient Duration NOT Causing Reset Pulse vs. Reset Threshold Overdrive. 13

MAXIMUM RATING. 14 Table 7. Absolute Maximum Ratings. 14 DC AND AC PARAMETERS. 14 Table 8. Operating and AC Measurement Conditions. 14 Figure 21.AC Testing Input/Output Waveforms. 14 Table 9. DC and AC Characteristics. 15 PACKAGE MECHANICAL. 16 Figure 3-lead Small Outline Transistor Package Outline. 17 Table 3-lead Small Outline Transistor Package Mechanical Data. 17 PART NUMBERING. 18 Table 11. Ordering Information Scheme. 18 Table 12. Marking Description. 19 REVISION HISTORY. 20 Table 13. Document Revision History. 20


 

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