Details, datasheet, quote on part number: PSD954570MIT
PartPSD954570MIT
CategoryMemory => Flash
DescriptionFlash In-system Programmable Isp Peripherals For 8-bit MCUs
CompanyST Microelectronics, Inc.
DatasheetDownload PSD954570MIT datasheet
  

 

Features, Applications
Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

2Mbit of Primary Flash Memory (8 uniform sectors, to 256Kbit Secondary Flash Memory (4 uniform sectors) to 256Kbit SRAM Over 3,000 Gates of PLD: DPLD and CPLD 27 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management High Endurance: 100,000 Erase/WRITE Cycles of Flash Memory 1,000 Erase/WRITE Cycles of PLD

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 3.0

TABLE OF CONTENTS SUMMARY DESCRIPTION. 8 Table 1. Product Range (Note 1). 8 KEY FEATURES. 9 Figure 3. PSD8XXFX Block Diagram. 10 PSD8XXFX ARCHITECTURAL OVERVIEW. 11 Memory. 11 Page Register. 11 PLDs. 11 Table 2. PLD I/O. 11 I/O Ports. 11 MCU Bus Interface. 11 JTAG Port. 12 In-System Programming (ISP). 12 Power Management Unit (PMU). 12 Table 3. JTAG SIgnals on Port C. 12 Table 4. Methods of Programming Different Functional Blocks of the PSD8XXFX. 12 DEVELOPMENT SYSTEM. 13 Figure 4. PSDsoft Express Development Tool. 13 PIN DESCRIPTION. 14 Table 5. Pin Description (for the PLCC52 package - Note 14 PSD8XXFX Register Description and Address Offset. 16 Table 6. I/O Port Latched Address Output Assignments (Note1). 17 Table 7. Register Address Offset. 17 DETAILED OPERATION. 18 MEMORY BLOCKS. 18 Primary Flash Memory and Secondary Flash memory Description. 18 Memory Block Select Signals. 18 Table 8. Instructions. 19 INSTRUCTIONS. 20 Power-down Instruction and Power-up Mode. 20

READ. 20 Table 9. Status Bit. 21 Programming Flash Memory. 22 Figure 5. Data Polling Flowchart. 22 Figure 6. Data Toggle Flowchart. 23 Erasing Flash Memory. 24 Specific Features. 25 Table 10. Sector Protection/Security Bit Definition Flash Protection Register. 25 Table 11. Sector Protection/Security Bit Definition PSD/EE Protection Register. 25 SRAM. 26 Sector Select and SRAM Select. 26 Figure 7. Priority Level of Memory and I/O Components. 26 Table 12. VM Register. 27 Figure 8. 8031 Memory Modules Separate Space. 27 Figure 9. 8031 Memory Modules Combined Space. 28 Page Register. 29 Figure 10. Page Register. 29 PLDS. 30 Table 13. DPLD and CPLD Inputs. 30 The Turbo Bit PSD8XXFX. 30 Figure 11. PLD Diagram. 31 Decode PLD (DPLD). 32 Figure 12. DPLD Logic Array. 32 Complex PLD (CPLD). 33 Figure 13. Macrocell and I/O Port. 33 Output Macrocell (OMC). 34 Table 14. Output Macrocell Port and Data Bit Assignments. 34 Product Term Allocator. 35 Figure 14. CPLD Output Macrocell. 36 Input Macrocells (IMC). 37 Figure 15. Input Macrocell. 38 Figure 16. Handshaking Communication Using Input Macrocells. 39 MCU BUS INTERFACE. 40 Table 15. MCUs and their Control Signals. 40 Figure 17. An Example of a Typical 8-bit Multiplexed Bus Interface. 41 Figure 18. An Example of a Typical 8-bit Non-Multiplexed Bus Interface. 42 Table 16. Eight-Bit Data Bus. 42


 

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