|Category||Timing Circuits => Clock Synthesizers|
|Description||High-frequency PLL Frequency Synthesizer|
|Datasheet||Download SK12429LV datasheet
The is a general purpose synthesized clock source targeting applications that require both serial and parallel interfaces. Its internal VCO will operate over a range of frequencies from to 800 MHz. The differential PECL output can be configured to be the VCO frequency divided or 16. With the output configured to divide the VCO frequency by 2, and with a 16.000 MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1 MHz steps. The PLL loop filter is fully integrated so that no external components are required. The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 8 before being sent to the phase detector. With a 16 MHz crystal, this provides a reference frequency of 2 MHz. Although this datasheet illustrates functionality only for a 16 MHz crystal, any crystal in the 10-20 MHz range can be used. The VCO within the PLL operates over a range to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interface. The output of this loop divider is also applied to the phase detector. The phase detector and loop filter attempt to force the VCO output frequency be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider (N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios or 16). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC 2.0V. The positive reference for the output driver and the internal logic is separated from the power supply for the phaselocked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally, on system reset, the P_LOAD* input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transition of P_LOAD*, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pull-up resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the chip. The serial interface centers a 14-bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold time as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information.Features
Operates from to 3.8V Power Supply to 400 MHz Differential PECL Outputs ±25 ps Peak-to-Peak Output Jitter Fully Integrated Phase-Locked Loop Minimal Frequency Over-Shoot Synthesized Architecture Serial 3-Wire Interface Parallel Interface for Power-Up Quartz Crystal Interface Available in 28-Lead PLCC Package ESD Protection of >4000V Operating Temperature Range: to 70oCTEST AND MEASUREMENT DIVISION Functional Block Diagram
Pin N ame XTAL1, XTAL2 S_LOAD (Int. Pull-down) S_DATA (Int. Pull-down) S_CLOCK (Int. Pull-down) P_LOAD* (Int. Pull-up) M[8:0] (Int. Pull-up) N[1:0] (Int. Pull-up) OE (Int. Pull-up) Ou FOUT, FOUT* TEST Pow er VCC PLL_VCC GND This is the positive supply for the internal logic (VCC1) and the output buffer of the chip (VCC0) is connected to +3.3V typically. This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter operation. This supply is connected to +3.3V typically. These pins are the negative supply for the chip and are normally all connected to ground. These differential positive-referenced ECL signals (PECL) are the output of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0]. These pins form an oscillator when connected to an external series-resonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latch will be transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD* for proper operation. These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD*. M is the MSB, M is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD*. Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation of the FOUT output. Fu n ction
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