|Category||Timing Circuits => Clock Generators|
|Description||Low Voltage 1:9 Differential Ecl/pecl Clock Driver|
|Datasheet||Download SK10LVE111E datasheet
|1:9 Differential LVECL/LVPECL Clock Driver w/Enable Input
The is a low skew 1-to-9 differential driver designed with clock distribution in mind. The SK10/ 100LVE111E's function and performance are similar to the SK100E111, with the added feature of low voltage operation and the enable input. It accepts one signal input which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A PECL High logic level disables the device by forcing all Q outputs Low and all Q* outputs High. The device is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure do so will result in small degradations of propagation delay (on the order 1020ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The SK10/100LVE111E, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111E's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage.Features
200 ps Part-to-Part Skew 50 ps Output-to-Output Skew Differential Design VBB Output Enable Input Voltage and Temperature Compensated Outputs Low Voltage VEE Range 3.8V 75K Internal Input Pulldown Resistors Fully Compatible with MC100LVE111 Specified Over Industrial Temperature Range: to 85oC ESD Protection of >4000V Available in 28-pin PLCC PackagePin IN, IN* EN* Q8, Q8* VBB.unction Differential Input Pair Enable Differential Outputs VBB Output
HIGH-PERFORMANCE PRODUCTS Package Information 28 Pin PLCC Package
NOTES: 1. Datums -L-, -M-, and -N- determined where top of lead shoulder exits plastic body at mold parting line. 2. DIM G1, true position to be measured at Datum -T-, Seating Plane. 3. DIM R and U do not include mold flash. Allowable mold flash 0.010 (0.250) per side. 4. Dimensioning and tolerancing per ANSI 1982. 5. Controlling Dimension: Inch. 6. The package top may be smaller than the package bottom 0.012 (0.300). Dimensions R and U are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. Dimension H does not include Dambar protrusion or intrusion. The Dambar protrusion(s) shall not cause the H dimension to be greater than 0.037 (0.940). The Dambar intrusion(s) shall not cause the H dimension to be smaller than 0.025 (0.635).
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