Details, datasheet, quote on part number: SK10EL38W
PartSK10EL38W
CategoryTiming Circuits => Clock Distribution => Clock Dividers
TitleClock Dividers
Description2, 4/6 Clock Generation Chip
CompanySemtech Corporation
DatasheetDownload SK10EL38W datasheet
Cross ref.Similar parts: SY10EL38Z
  

 

Features, Applications

The 4/6 Clock Generation Chip designed explicitly for low skew clock generation applications. The SK10/100EL38W is fully compatible with MC100EL38 and MC100LVEL38. The internal dividers are synchronous to each other; therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or singleended ECL/LVECL or, if positive power supply is used, PECL/LVPECL input signal. The VBB output is provided for single-ended use a DC bias for AC coupling to the device. VBB is an output and should be used as a bias for the SK10/100EL38W as its current source/ sink capability is limited. Whenever used, the VBB output should be bypassed to ground via 0.01 F capacitor. The Common Enable (EN*) input is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. This avoids any chance of generating any runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. The Phase_Out output will go high for one clock cycle whenever the 2, 4/6 output are both transitioning from a LOW to a HIGH. This output allows for clock synchronization within the system. Upon start-up, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EL38Ws, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EL38W, the MR pin need not to be exercised as the internal divider design ensures synchronization between the 2 and the 4/6 outputs of a single device.

Extended Supply Voltage Range (VEE to 3.0V, VCC 0V) or (VCC to +3.0V, VEE = 0V) High Bandwidth Output Transition 50 ps Output-to-Output Skew Master Reset for Synchronization VBB Output Internal Input Pulldown Resistor New Differential Input Common Mode Range Fully Compatible with MC100EL38 and MC100LVEL38 ESD Protection of >4000V Industrial Temperature Range: to +85oC Available in 20 Pin SOIC Package

Differential Clock Inputs Synchronous Enable Master Reset Reference Output Voltage Differential2 Outputs Diff4/6 Outputs Frequency Select Input Phase Sync Signal

AN1002 - Interfacing Between ECL / LVECL / PECL / LVPECL to - TTL / LVTTL / CMOS / LVCMOS AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices AN1005 - Using ECL / LVECL Devices as PECL / LVPECL AN1006 - Designing with 10K and 100K ECL / PECL Devices

HIGH-PER.ORMANCE PRODUCTS Package Information 20 Pin SOIC Package

NOTES: 1. Dimensions and tolerances per ASME 1994. 2. Controlling dimension: millimeters. 3. Dimensions D and E do not include mold protrusion. 4. Maximum mold protrusion 0.15 per side. 5. Dimension B does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.13 total in excess of B dimension at maximum material condition.


 

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