|Category||Logic => Clock Drivers/Distribution|
|Description||1:4 Clock Distribution|
|Datasheet||Download SK10EL15WD datasheet
The is a low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. This device is fully compatible with & MC100EL15. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input to be used, the VBB output should be connected to the CLK* input and bypassed to VCC via 0.01 µF capacitor. The EL15W provides a VBB output for either single-ended use a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for EL15W as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to VCC via 0.01 µF capacitor. The EL15W features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN*) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.
Extended Supply Voltage Range: (VEE to 3.0V, VCC 0V) or (VCC 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input 75K Internal Input Pull-Down Resistors Fully Compatible with MC10EL15 and MC100EL15 Specified Over Industrial Temperature Range: to +85oC ESD Protection of >4000V Available in 16-Pin SOIC Package
Pin Name CLK SCLK EN* SEL VBB Q0Q3, Q0*-Q3*.unction Differential Clock Inputs Synchronous Clock Input Synchronous Enable Clock Select Input Reference Output Voltage Differential Clock Outputs
*On next negative transition of CLK or SCLK. Truth Table
NOTES: 1. Dimensioning and tolerancing per ANSI 1982. 2. Controlling dimension: millimeter. 3. Dimensions A and B do not include mold protrusion. 4. Maximum mold protrusion 0.150 (0.006) per side. 5. Dimension D does not include Dambar protrusion. Allowable Dambar protrusion shall 0.13 (0.005) total in excess of d dimension at maximum material condition.
Ch nput Cur r ent ( Di SE) Power Supply Cur rent 10EL 100EL Output Reference 10EL 100EL Power Supply Voltage
Symbol Characteristic t PLH P HL tskew tS tH VPP , tf Propagation Delay f ) CLK SE) SCLK o Q Par t-to-Par t Skew Within-Device SkeW i mu mmo n Mo
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