Details, datasheet, quote on part number: M377S6450AT3-C1L
PartM377S6450AT3-C1L
CategoryMemory => DRAM => SDR SDRAM => Modules => Registered DIMM
TitleRegistered DIMM
DescriptionDescription = M377S6450AT3 (Intel 1.2 Ver Base) 64Mx72 Sdram Dimm With PLL & Register Based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 1H,1L ;; #of Pin = 168 ;; Power = C ;; Component Composition = (64Mx4)x18+Drive ICx3+PLL+EEPROM ;; Production Status = Eol ;; Comments = PC100
CompanySamsung Semiconductor, Inc.
DatasheetDownload M377S6450AT3-C1L datasheet
  

 

Features, Applications

64Mx72 SDRAM DIMM with PLL & Register based 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD

The Samsung a 64M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M377S6450AT3 consists of eighteen CMOS 64Mx4 bit Synchronous DRAMs in TSOP-II 400mil packages, three 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect a 168-pin glass-epoxy substrate. Two 0.22uF and one 0.0022uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The is a Dual In-line Memory Module and is intented for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURE

Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,700mil), double sided component

Pin Front VSS DQ2 DQ3 VDD DQ7 DQ8 VSS DQ12 DQ13 VDD CB0 CB1 VSS NC VDD WE DQM0 Pin Front Pin Front DQ18 DQ19 VDD DQ20 NC *VREF *CKE1 VSS DQ22 DQ23 VSS DQ26 DQ27 VDD DQ30 DQ31 VSS NC WP **SDA **SCL VDD Pin Back Pin Back DQM5 *CS1 RAS VSS BA0 A11 VDD *CLK1 A12 VSS DQM7 *A13 VDD CB6 CB7 VSS DQ48 DQ49 Pin Back 60 32 VSS 68 40 VDD 69 41 VDD 71 43 VSS 77 49 VDD 82 54 VSS DQ17 84 VSS 89 DQ35 VDD 95 DQ40 VSS DQ45 102 VDD 106 CB5 VSS 109 110 VDD 111 CAS DQ51 143 VDD 145 146 *VREF 147 REGE 148 VSS DQ55 152 VSS DQ59 157 VDD DQ63 162 VSS **SA2 168 VDD

Pin Name CS0, CS2 RAS CAS ~ 7 VDD VSS *VREF REGE SDA SCL NC WP Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Write protection

* These pins are not used in this module. These pins should NC in the system which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address ~ RA12, Column address CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. WP pin is connected to VSS through 47K Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.

Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask

Data input/output Check bit Write protection Power supply/ground

DQ0~3 10 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM 10 PCLK1 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM PCLK3 BCS2 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM 10 PCLK5 CLK CS CKE Add,CTL DQM DQ0~3

CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3


Note 1. Unused clock termination : 10 and 12pF 2. The actual values of Cb will depend upon the PLL chosen.


 

Related products with the same datasheet
M377S6450AT3-C1H
Some Part number from the same manufacture Samsung Semiconductor, Inc.
M377S6450BT3 Description = M377S6450BT3 (Intel 1.2 Ver Base) 64Mx72 Sdram Dimm With PLL & Register Based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/
M377S6450CT3
M377S6450DT3 Description = M377S6450DT3 64M X 72 Sdram Dimm With PLL & Register Based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/ Interface = 4B/LVTTL
M377S6453AT0 Description = M377S6453AT0 (Intel 1.2 Ver Base) 64Mx72 Sdram Dimm With PLL & Register Based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/
M377S6453BT0 Description = M377S6453BT0 (Intel 1.2 Ver Base) 64Mx72 Sdram Dimm With PLL & Register Based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/
M377S6453CT0 Description = M377S6453CT0 64M X 72 Sdram Dimm With PLL & Register Based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/ Interface = 4B/LVTTL
M377S6453DT0 Description = M377S6453DT0 (Intel 1.2 Ver Base) 64Mx72 Sdram Dimm With PLL & Register Based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/
M381L1713BT0 Description = M381L1713BT0 16Mx72 DDR Sdram 184pin Dimm Based on 16Mx8 ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power
M381L1713BT1 Description = M381L1713BT1 16Mx72 DDR Sdram 184pin Dimm Based on 16Mx8 ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = A0,A2,B0 ;; #of Pin = 184 ;; Power
M381L1713CT1
M381L1713CTL Description = M381L1713CTL 16Mx72 DDR Sdram 184pin Dimm Based on 16Mx8 ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = A0,A2,B0 ;; #of Pin = 184 ;; Power
M381L1713DTL Description = M381L1713DTL 16Mx72 DDR Sdram 184pin Dimm Based on 16Mx8 ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = B3,A2,B0,A0 ;; #of Pin = 184 ;; Power
M381L1713DTM Description = M381L1713DTM 16M X 72 DDR Sdram 184pin Dimm Based on 16M X 8 ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = B3 ;; #of Pin = 184 ;; Power
M381L1713ETM Description = M381L1713ETM 184Pin Unbuffered Dimm Based on 128Mb E-die (x8) ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = CC,C4,B3,AA,A2,B0
M381L2923BTM Description = M381L2923BTM 184Pin Unbuffered Dimm Based on 512Mb B-die (x8, X16) ;; Density(MB) = 1024 ;; Organization = 128Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0
M381L2923MT1
M381L2923MTL Description = M381L2923MTL 128Mx72 DDR Sdram 184pin Dimm Based on 64Mx8 ;; Density(MB) = 1024 ;; Organization = 128Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power
M381L3223AT0 Description = M381L3223AT0 32Mx72 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 256 ;; Organization = 32Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power
M381L3223BT0 Description = M381L3223BT0 32Mx72 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 256 ;; Organization = 32Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power
M381L3223BT1 Description = M381L3223BT1 32M X 72 DDR Sdram 184pin Dimm Based on 32M X 8 ;; Density(MB) = 256 ;; Organization = 32Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A0,A2,B0 ;; #of Pin = 184 ;; Power
M381L3223CT1 Description = M381L3223CT1 32Mx72 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 256 ;; Organization = 32Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; #of Pin = 184 ;; Power

K7R641884M-FC16 : QDR I/II Description = K7R641884M 2Mx36-bit, 4Mx18-bit, 8Mx8-bit QDR™ Ii b4 SRAM ;; Organization = 4Mx18 ;; VDD(V) = 1.8 ;; Access Time-tCD(ns) = - ;; Cycle Time(MHz) = 300,250,200,167 ;; I/o Voltage(V) = - ;; Package = 165FBGA ;; Production Status = Engineering Sample(2Q,'04) ;; Comments = -

KM23V64015BF : 64M bit Description = KM23V64015B 64M-Bit(8Mx8,4Mx16) CMOS Mask ROM ;; Organization = 8Mx8,4Mx16 ;; Voltage(V) = 3,1.8(Vccq=1.8V) ;; Speed(ns) = 120/40(Max.)@CL=100pF ;; Package = 48FBGA ;; Current (mA/uA) = 60/30 ;; Production Status = Mass Production ;; Comments = -

KM616FR1010T : Description = KM616FR1010 64K X16 Bit Super Low Power And Low Voltage Full CMOS Static RAM ;; Organization = 64Kx16 ;; Vcc(V) = 1.8~2.7 ;; Speed-tAA(ns) = 300 ;; Operating Temperature = 0~70,-40~85 ;; Operating Current(mA) = 20 ;; Standby Current(uA) = 5 ;; Package = 44TSOP2 ;; Production Status = E

M364E1600BJ0-C : Buffered DIMM Description = M364E1600BJ0 16Mx64 DRAM Dimm Using 16Mx4,4K&8K Refresh,5V ;; Density(MB) = 128 ;; Organization = 16Mx64 ;; Mode = Edo ;; Refresh = 4K/64ms ;; Speed(ns) = 50,60 ;; #of Pin = 168 ;; Component Composition = (16Mx4)x16+Drive ICx2 ;; Production Status = Eol ;; Comments = Buffered

KFG4G16Q2M-DEB5 : Flash Memory(54mhz)

K4E661612C-45 : 4M x 16bit CMOS Dynamic RAM with Extended Data Out

AT-LC-A-M5-04-C : RF/MICROWAVE FIXED ATTENUATOR, 20 dB INSERTION LOSS-MAX Specifications: Attenuator Type: Fixed ; Insertion Loss: 20 dB ; Attenuation: 1 dB

K8A6215EBC-DC7B0 : 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA88 Specifications: Memory Category: Flash, PROM ; Density: 67109 kbits ; Number of Words: 4000 k ; Bits per Word: 16 bits ; Package Type: 8 X 11 MM, 1.10 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-88 ; Pins: 88 ; Logic Family: CMOS ; Supply Voltage: 1.8V ; Access Time: 70 ns ; Operating Temperature: 0 t

 
0-C     D-L     M-R     S-Z