Details, datasheet, quote on part number: M377S3253CT3
PartM377S3253CT3
CategoryMemory => DRAM => SDR SDRAM => Modules => Registered DIMM
TitleRegistered DIMM
DescriptionDescription = M377S3253CT3 (Intel 1.2 Ver Base) 32Mx72 Sdram Dimm With PLL & Register Based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 256 ;; Organization = 32Mx72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 1H,1L ;; #of Pin = 168 ;; Power = C ;; Component Composition = (32Mx8)x9+EEPROM ;; Production Status = Eol ;; Comments = PC100
CompanySamsung Semiconductor, Inc.
DatasheetDownload M377S3253CT3 datasheet
  

 

Features, Applications

32Mx72 SDRAM DIMM with PLL & Register based 4Banks 8K Ref., 3.3V Synchronous DRAMs with SPD

The Samsung a 32M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M377S3253CT3 consists of nine CMOS 32Mx8 bit Synchronous DRAMs in TSOP-II 400mil packages, two 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect a 168pin glass-epoxy substrate. Two 0.22uF and one 0.0022uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The is a Dual In-line Memory Module and is intented for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURE

Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,500mil), double sided component

Pin Front VSS DQ2 DQ3 VDD DQ7 DQ8 VSS DQ12 DQ13 VDD CB0 CB1 VSS NC VDD WE DQM0 Pin Front Pin Front DQ18 DQ19 VDD DQ20 NC *VREF *CKE1 VSS DQ22 DQ23 VSS DQ26 DQ27 VDD DQ30 DQ31 VSS *CLK2 NC *WP **SDA **SCL VDD Pin Back Pin Back DQM5 *CS1 RAS VSS BA0 A11 VDD *CLK1 A12 VSS DQM7 *A13 VDD CB6 CB7 VSS DQ48 DQ49 Pin Back 60 32 VSS 68 40 VDD 69 41 VDD 71 43 VSS 77 49 VDD 82 54 VSS DQ17 84 VSS 89 DQ35 VDD DQ40 96 VSS DQ45 102 VDD CB5 107 VSS 109 110 VDD 111 CAS DQ51 143 VDD 145 146 *VREF 147 REGE VSS 151 DQ55 VSS DQ59 157 VDD DQ63 162 VSS **SA2 168 VDD

Pin Name CS0, CS2 RAS CAS ~ 7 VDD VSS *VREF REGE SDA SCL DU NC *WP Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Write protection

* These pins are not used in this module. These pins should NC in the system which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address ~ RA12, Column address ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. Power and ground for the input buffers and the core logic.

Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask


Notes : Address/Control Signals are connected to D2 through 100 ohms resistor.

A0~A9 RAS,CAS,WE DQM0,1,4,5 CS0 REGE PCLK2 10k VDD BDQM2,3,6,7 * Note 1. Unused clock termination : 10 and 12pF 2. The actual values of Cb will depend upon the PLL chosen. SN74ALVCF162835 B0A0~B0A9 BRAS,BCAS,BWE LE OE


 

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