|Category||Interface and Interconnect|
|Description||Bcd-to-7 Segment Latch/decoder/driver For Liquid Crystals|
|Datasheet||Download MC14543B datasheet
|Cross ref.||Similar parts: MC14543BCP, MC14543BD, MC14543BDR2, MC14543BF|
The MC14543B BCDtoseven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is constructed with complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions a 4bit storage latch and an 8421 BCDtoseven segment decoder and driver. The device has the capability to invert the logic levels of the output combination. The phase (Ph), blanking (BI), and latch disable (LD) inputs are used to reverse the truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to the Ph input of the circuit and the electrically common backplane of the display. The outputs of the circuit are connected directly to the segments of the LC readout. For other types of readouts, such as lightemitting diode (LED), incandescent, gas discharge, and fluorescent readouts, connection diagrams are given on this data sheet. Applications include instrument (e.g., counter, DVM etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses.
PDIP16 P SUFFIX CASE 648 MC14543BCP AWLYYWW SOIC16 D SUFFIX CASE SOEIAJ16 F SUFFIX CASE 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week MC14543B ALYW 14543B AWLYWW
Latch Storage of Code Blanking Input Readout Blanking on All Illegal Input Combinations Direct LED (Common Anode or Cathode) Driving Capability Supply Voltage Range 18 V Capable of Driving 2 Lowpower TTL Loads, 1 Lowpower Schottky TTL Load or 2 HTL Loads Over the Rated Temperature Range PinforPin Replacement for CD4056A (with Pin 7 Tied to VSS). Chip Complexity: 207 FETs or 52 Equivalent GatesMAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin Iin PD TA Tstg IOHmax IOLmax POHmax POLmax Parameter DC Supply Voltage Range Input Voltage Range, All Inputs DC Input Current per Pin Power Dissipation, per Package (Note 3.) Operating Temperature Range Storage Temperature Range Maximum Continuous Output Drive Current (Source or Sink) Maximum Continuous Output Power (Source or Sink) (4.) Value 0.5 to VDD +150 10 (per Output) 70 (per Output) Unit mA mW
Device MC14543BF MC14543BFEL Package SOIC16 SOEIAJ16 Shipping 2500/Tape & Reel See Note 1. See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Publication Order Number: MC14543B/D
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 125_C 4. POHmax = IOH (VOH VDD) and POLmax = IOL (VOL VSS)
X = Don't care = Above Combinations * = For liquid crystal readouts, apply a square wave to Ph For common cathode LED readouts, select = 0 For common anode LED readouts, select 1 = Depends upon the BCD code previously applied when = 1
5. Noise immunity specified for worstcase input combination. Noise Margin for both "1" and "0" level 1.0 V min @ VDD 2.0 V min @ VDD 2.5 V min @ VDD 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) x 103 (CL 50) VDDf where: in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. 7. The formulas given are for the typical characteristics only at 25_C.
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