Details, datasheet, quote on part number: CMOS-8LCX
PartCMOS-8LCX
CategoryASICs => Gate Array
TitleGate Array
Description3-v, 0.50-micron CMOS Gate Arrays Crosscheck Test Support
CompanyNEC Electronics Inc.
DatasheetDownload CMOS-8LCX datasheet
  

 

Features, Applications
Description

NEC's 3-volt CMOS-8LCX family consists of ultra-high performance, sub-micron gate arrays, targeted for applications requiring extensive integration and high speeds. The device processing includes a true 3-volt, 0.5-micron (drawn) silicon-gate CMOS technology and three-layer metalization. This technology features channelless (sea-of-gates) architecture with an internal gate delay 131 ps (F/O = 0 mm). The PD658xx series of 3-volt CrossCheck-supported devices consists of 10 masters, offered in densities of 10K gates to 486K gates. Usable gates range from 32K gates to 389K gates. These gate arrays are ideal for use in engineering workstations, high-end PCs, mainframes and LAN products, where extensive integration and high speed are primary design goals. CMOS-8LCX gate arrays are also well-suited for all battery-operated applications where high performance and low power consumption are critical; and feasible only with a truly optimized 3-volt CMOS process.

3-VOLT, 0.50-MICRON CMOS GATE ARRAYS CROSSCHECK TEST SUPPORT
Features

Supports CrossCheck on-chip testability circuitry Internal gate delays 131 ps (F/O = 0 mm) Channelless, 0.50 m CMOS architecture Power (typ.) 0.80 (3.0V) Process technology designed for 3V operation I/Os interface directly to 5V logic 48mA GTL I/O buffers are in development Phase Locked Loop (PLL) for chip-to-chip clock synchronization in development Automated generation of clock network for skew minimization High pad to gate ratio optimizes silicon usage Fully configurable high-speed RAM compiler Advanced package options include TAB/QFP, TQFP, PQFP, PGA and TAB Libraries characterized at 3V10% and 3.3V0.3V Variable output drive: 48 mA Slew-rate controlled output buffers Supports scan test methodology Single/Dual-Port RAM and ROM memory blocks

Actual gate utilitization may vary depending on circuit implementation. Utilization is 70% for three-layer metal. Depending on package and circuit specification, some pads are used for VDD and GND and are not available as signal pads.

CMOS-8LCX products are fully supported by NEC's advanced ASIC design technology. NEC's OpenCAD integration system lets the designer choose the most powerful design tools and services available. CMOS-8LCX gate arrays support automatic test generation through CrossCheck Technology's testability structures. This results in high fault coverage ATPT of synchronous and asynchronous designs with no netlist modifications and without designer involvement.

OpenCAD is a registered trademark of NEC Electronics Inc. CrossCheck is a registered trademark of CrossCheck Technology, Inc.

CMOS-8LCX products are built with NEC's 0.50-micron (drawn) channelless gate array architecture. As shown in figure 2, CMOS gate array chips are divided into I/O and internal cell areas. The I/O cell area contains input and output buffers that isolate the internal cells from high-energy external signals. The internal cell area is an array of basic cells, each composed of two p-channel MOS transistors and two n-channel MOS transistors, as well as four additional n-channel MOS transistors for compact RAM design. A cell configured as a two-input NAND gate is shown in figure 3. These p-channel and n-channel transistors are sized to offer a superb ratio of speed to silicon area.

Fast rise and fall times of CMOS output buffers can cause system noise and signal overshoot. When an unterminated line is being driven by a buffer, the maximum line length is determined by the rise and fall time of the output buffers and the round-trip signal delay of the line.

As a general rule, the round-trip delay of the line should not exceed the rise or fall time of the driving signal. Transmission lines that are longer than those determined by this rule can degrade system performance due to reflections and ringing. One benefit of slew-rate output buffers is that longer interconnections a PC board and routing flexibility are possible. ASIC designers, therefore, can slow down the output edge-rate by using a slew-rate output buffer and thus accommodate longer transmission lines on PC boards. Slew-rate buffers also inject less noise into the internal power and ground busses of the device, than their nonslew-rate counterparts. As a consequence, slew-rate buffers require fewer power/ground pairs for simultaneous switching outputs.

Figure 2. Chip Layout and Internal Cell Configuration

This data sheet contains preliminary specifications, package information, and operational data for the CMOS-8LCX gate array families. Additional design information will be available in NEC's CMOS-8LCX Block Library and CMOS-8LCX Design Manual. Contact your local NEC Design Center or the NEC Literature Center for further ASIC design information; see the back of this data sheet for locations and phone numbers.

Power supply voltage, DD 3V interface I/O voltage, VO 5V interface I/O voltage, , VO Latch-up current, I LATCH Operating temperature, TOPT Storage temperature, TSTG V to VDD V to VDD >1 A (typ) to +150C

VDD = 1 MHz Terminal Input Output I/O Symbol CIN COUT CI/O Typ 10 Max 20 Unit pF

Caution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions.

Description Internal cell Input block (FI01) Output block Limits 10.0 0.181 Unit W/MHz mW/MHz

Parameter Power supply voltage Ambient temperature Low-level input voltage, 3V High-level input voltage, 3V Low-level input voltage, 5V High-level input voltage, 5V Input rise or fall time Input rise or fall time, Schmitt Positive Schmitt-trigger voltage Negative Schmitt-trigger voltage Hysteresis voltage Symbol VDD TA VIL VIH VIL V IH tR, tF tR, VN VH Min VDD TBD Max +85 0.3 VDD 0.8 VPP 200 10 TBD Unit ms V

Parameter Toggle frequency Delay time, 2-input NAND gate Standard gate (F302) tPD 131 243 Low power gate 149 371 Delay time, buffer Input (FI01) Output (FO06) Output rise time (FO06) Output fall time (FO06) tPD tF ns F/O mm @ VDD pF @ VDD pF @ VDD pF @ VDD 3.3V ps F/O 0 mm F/O 1 mm F/O 0 mm F/O 1 mm Symbol fTOG Min 175 Typ Max Unit MHz Conditions D -F/F; F/O = 2


 

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