Details, datasheet, quote on part number: MCM62486BFN19
PartMCM62486BFN19
Category
Description32k X 9 Bit Burstram Synchronous Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM62486BFN19 datasheet
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Features, Applications

The a 294,912 bit synchronous static random access memory designed to provide a burstable, high­performance, secondary cache for the i486 and PentiumTM microprocessors. It is organized as 32,768 words of 9 bits, fabricated with Motorola's high­performance silicon­gate CMOS technology. The device integrates input registers, a 2­bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses ­ A14), data inputs ­ D8), and all control signals except output enable (G) are clock (K) controlled through positive­edge­triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM62486B (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self­timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off­chip write pulse generation and provides increased flexibility for incoming signals. The MCM62486B will be available a 44­pin plastic leaded chip carrier (PLCC). Multiple power and ground pins have been utilized to minimize effects induced by output noise. Separate power and ground pins have been employed for DQ8 to allow user­controlled output levels of 5 volts or 3.3 volts. Single ± 10% Power Supply 5% for MCM62486BFN11) Choice ± 10% Power Supplies for Output Level Compatibility Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min Internal Input Registers (Address, Data, Control) Internally Self­Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three­State Outputs Common Data Inputs and Data Outputs High Output Drive Capability: 85 pF per I/O High Board Density PLCC Package Fully TTL­Compatible Active High and Low Chip Select Inputs for Easy Depth Expansion

A1 A0 ADV ADSC ADSP A5 A6 VSS DQ0 DQ1 VSSQ VCCQ DQ3 V SSQ DQ8 V SSQ A13 A14 VSS DQ7 DQ6 VSSQ VCCQ DQ5 DQ4

­ A14. Address Inputs K. Clock W. Write Enable G. Output Enable S0, S1. Chip Selects ADV. Burst Address Advance ADSP, ADSC. Address Status ­ DQ8. Data Input/Output VCC. 5 V Power Supply VCCQ. Output Buffer Power Supply VSS. Ground VSSQ. Output Buffer Ground All power supply and ground pins must be connected for proper operation of the device. VCC VCCQ at all times including power up.

BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp.
ADV BURST LOGIC Q0 BINARY COUNTER Q1 A1 INTERNAL A0 ADDRESS x 9 MEMORY ARRAY

NOTE: All registers are positive­edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the

next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent W) is performed using the new external address. Chip selects (S0, S1) are sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE.

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0
NOTE: The burst wraps around to its initial state upon completion.

ADSP ADSC ADV L­H Address Used N/A External Address External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst

NOTES: 1. X means Don't Care. 2. All inputs except G must meet setup and hold times for the low­to­high transition of clock (K). 3. S represents S0 and S1. T implies = L and H; F implies L. 4. Wait states are inserted by suspending burst.

Operation Read Write Deselected I/O Status Data Out ­ DQ8) High­Z Data ­ DQ8) High­Z

NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.

Rating Power Supply Voltage Output Power Supply Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC VCCQ Vin, Vout Iout PD Tbias TA Value 0.5 to VCC 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high­impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

Storage Temperature Tstg 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.


 

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