Details, datasheet, quote on part number: MCM6227BJ17
Description1m X 1 Bit Static Random Access Memory
CompanyMotorola Semiconductor Products
DatasheetDownload MCM6227BJ17 datasheet
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Features, Applications

The a 1,048,576 bit static random­access memory organized as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227B is each equipped with a chip enable (E) pin. This feature provides reduced system power requirements without degrading access time performance. The MCM6227B is available in 300 mil and 400 mil, 28­lead surface­mount SOJ packages. Single ± 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three­State Output Low Power Operation: 115/110/105/100/95 mA Maximum, Active AC

A A. Address Inputs W. Write Enable E. Chip Enable D. Data Input Q. Data Output NC. No Connection VCC. 5 V Power Supply VSS. Ground *If not used for no connect, then do not exceed voltages 0.5 to VCC 0.5 V. This pin is used for manufacturing diagnostics.

Mode Not Selected Read Write I/O Pin High­Z Dout High­Z Cycle Read Write Current ISB1, ISB2 ICCA

Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high­impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

Storage Temperature Tstg 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.


Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) 0.5 V dc; VIL (min) V ac (pulse width 20 ns). VIH (max) = VCC 0.3 V dc; VIH (max) = VCC V ac (pulse width 20 ns). Symbol VCC VIH VIL Min Max 5.5 VCC +0.3** 0.8 Unit V

Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (E = VIH, Vout 0 to VCC) AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227B­15: tAVAV ns MCM6227B­17: tAVAV ns MCM6227B­20: tAVAV ns MCM6227B­25: tAVAV ns MCM6227B­35: tAVAV ns AC Standby Current (VCC = max, E = VIH, f fmax) MCM6227B­15: tAVAV ns MCM6227B­17: tAVAV ns MCM6227B­20: tAVAV ns MCM6227B­25: tAVAV ns MCM6227B­35: tAVAV 35 ns CMOS Standby Current (E VCC 0.2 V, Vin VSS V or VCC 0.2 V, VCC = max, = 0 MHz) Output Low Voltage (IOL + 8.0 mA) Output High Voltage (IOH ­ 4.0 mA) ISB2 VOL VOH mA V Symbol Ilkg(I) Ilkg(O) ICCA mA Min Max ±1 Unit µA mA

CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic Input Capacitance Input and Output Capacitance All Inputs Except Clocks and Q E and D, Q Symbol Cin Cin, Cout Typ 4 5 Max 6 8 Unit pF

Input Pulse Levels. 3.0 V Input Rise/Fall Time. 2 ns Input Timing Measurement Reference Level. 1.5 V Output Timing Measurement Reference Level. 1.5 V Output Load. See Figure 1a

6227B­15 Parameter Read Cycle Time Address Access Time Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High­Z Symbol tAVAV tAVQV tELQV tAXQX tELQX tEHQZ Min 15 5 Max 6 6227B­17 Min 17 5 Max 7 6227B­20 Min 20 5 Max 7 6227B­25 Min 25 5 Max 8 6227B­35 Min 35 5 Max 35 8 Unit ns Notes 2, 3

NOTES: W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady­state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL).

= 50 OUTPUT 1.5 V OUTPUT pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.


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