Details, datasheet, quote on part number: MCM6227A
Description1m X 1 Bit Static Random Access Memory
CompanyMotorola Semiconductor Products
DatasheetDownload MCM6227A datasheet
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Features, Applications

The a 1,048,576 bit static random­access memory organized as 1,048,576 words of 1 bit, fabricated using high­performance silicon­gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low­power standby mode, remaining in that state until E goes low again. The MCM6227A is available in 400 mil, 28­lead surface­mount SOJ packages. Single ± 10% Power Supply Fast Access Times: 25, 35, and 45 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three­State Output Low Power Operation: 160/140/130/120 mA Maximum, Active AC

­ A19. Address Inputs W. Write Enable E. Chip Enable D. Data Input Q. Data Output NC. No Connection VCC. 5 V Power Supply VSS. Ground

Mode Not Selected Read Write I/O Pin High­Z Dout High­Z Cycle Read Write Current ISB1, ISB2 ICCA

Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high­impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

Storage Temperature Tstg 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.


Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) 0.5 V dc; VIL (min) V ac (pulse width 20 ns). VIH (max) = VCC 0.3 V dc; VIH (max) = VCC V ac (pulse width 20 ns). Symbol VCC VIH VIL Min Max 5.5 VCC 0.3** 0.8 Unit V

Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (E = VIH, Vout 0 to VCC) AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227A­20: tAVAV ns MCM6227A­25: tAVAV ns MCM6227A­35: tAVAV ns MCM6227A­45: tAVAV ns AC Standby Current (VCC = max, E = VIH, f = fmax) CMOS Standby Current (E VCC 0.2 V, Vin VSS V or VCC 0.2 V, VCC = max, = 0 MHz) Output Low Voltage (IOL + 8.0 mA) Output High Voltage (IOH ­ 4.0 mA) * Typical values are measured at 25°C, VCC 5 V. Symbol Ilkg(I) Ilkg(O) ICCA ISB1 ISB2 VOL VOH mA V Min Typ* Max ±1 Unit µA mA

CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic Input Capacitance Input and Output Capacitance All Inputs Except Clocks and Q E and D, Q Symbol Cin Cin, Cout Typ 4 5 Max 6 8 Unit pF

Input Pulse Levels. 3.0 V Input Rise/Fall Time. 2 ns Input Timing Measurement Reference Level. 1.5 V Output Timing Measurement Reference Level. 1.5 V Output Load. See Figure 1A

6227A­20 Parameter Read Cycle Time Address Access Time Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High­Z Power Up Time Power Down Time Symbol tAVAV tAVQV tELQV tAXQX tELQX tEHQZ tELICCH tEHICCL Min Max 6227A­25 Min Max 6227A­35 Min Max 6227A­45 Min Max Unit ns Notes 2,3

NOTES: W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady­state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL).

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.


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