|Description||128k X 8 Bit Static Random Access Memory|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MCM6226BB datasheet
The a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6226BB is equipped with both chip enable (E1 and E2) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6226BB is available in 300 mil and 400 mil, 32 lead surfacemount SOJ packages. Single ± 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times All Inputs and Outputs are TTL Compatible Three State Outputs Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC BLOCK DIAGRAM
A. Address Inputs W. Write Enable G. Output Enable E1, E2. Chip Enables DQ. Data Inputs/Outputs NC. No Connection VCC. 5 V Power Supply VSS. Ground
E1 E2 Mode Not Selected Not Selected Output Disabled Read Write I/O Pin HighZ Dout Din Cycle Read Write Current ISB1, ISB2 ICCA
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these highimpedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature Tstg 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.(VCC to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) 0.5 V dc; VIL (min) V ac (pulse width 20 ns). VIH (max) = VCC 0.3 V dc; VIH (max) = VCC V ac (pulse width 20 ns). Symbol VCC VIH VIL Min Max 5.5 VCC 0.3** 0.8 Unit V
Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (E* = VIH, Vout 0 to VCC) AC Active Supply Current (Iout = 0 mA, all inputs = VIL or VIH, VIL = 0, VIH 3 V, cycle time tAVAV min, VCC = max) MCM6226BB15: tAVAV ns MCM6226BB17: tAVAV ns MCM6226BB20: tAVAV ns MCM6226BB25: tAVAV ns MCM6226BB35: tAVAV ns MCM6226BB15: tAVAV ns MCM6226BB17: tAVAV ns MCM6226BB20: tAVAV ns MCM6226BB25: tAVAV ns MCM6226BB35: tAVAV 35 ns Symbol Ilkg(I) Ilkg(O) ICCA Min 2.4 Max Unit µA mAAC Standby Current (VCC = max, E* = VIH, f = fmax)
CMOS Standby Current (E* VCC 0.2 V, Vin VSS V or VCC 0.2 V, VCC = max, = 0 MHz) Output Low Voltage (IOL + 8.0 mA) Output High Voltage (IOH 4.0 mA) *E1 and E2 are represented E in this data sheet. is of opposite polarity to E1.CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance I/O Capacitance All Inputs Except Clocks and DQs E2, G, and W DQ Symbol Cin Cck CI/O Typ 4 5 Max 6 8 Unit pF
Input Pulse Levels. 3.0 V Input Rise/Fall Time. 2 ns Input Timing Measurement Reference Level. 1.5 V Output Timing Measurement Reference Level. 1.5 V Output Load. See Figure 1a
6226BB15 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output HighZ Output Enable High to Output HighZ Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ Min Max 6226BB17 Min Max 6226BB20 Min Max 6226BB25 Min Max 6226BB35 Min Max Unit ns Notes 4
NOTES: W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. E1 and E2 are represented E in this data sheet. is of opposite polarity E1. 4. All timings are referenced from the last valid address to the first transitioning address. 5. Addresses valid prior to or coincident with E going low. 6. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 7. Transition is measured 500 mV from steadystate voltage with load of Figure 1b. 8. This parameter is sampled and not 100% tested. 9. Device is continuously selected (E VIL, G VIL).
+5 V OUTPUT 1.5 V OUTPUT pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
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