Details, datasheet, quote on part number: MCM62110FN15
PartMCM62110FN15
CategoryLogic
Description32k X 9 Bit Synchronous Dual I/o or Separate I/o Fast Static RAM With Parity Checker
CompanyMotorola Semiconductor Products
DatasheetDownload MCM62110FN15 datasheet
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Features, Applications

x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

The a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola's high­performance silicon­gate CMOS technology. The device integrates x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers, two sets of output latches, active high and active low chip enables, and a parity checker. The RAM checks odd parity during RAM read cycles. The data parity error (DPE) output is an open drain type output which indicates the result of this check. This device has increased output drive capability supported by multiple power pins. In addition, the output levels can be either 5 V TTL compatible by choice of the appropriate output bus power supply. The device has both asynchronous and synchronous inputs. Asynchronous inputs include the processor output enable (POE), system output enable (SOE), and the clock (K). The address ­ A14) and chip enable (E1 and E2) inputs are synchronous and are registered on the falling edge of K. Write enable (W), processor input enable (PIE) and system input enable (SIE) are registered on the rising edge of K. Writes to the RAM are self­timed. All data inputs/outputs, ­ SDQ7, PDQP, and SDQP have input data registers triggered by the rising edge of the clock. These pins also have three­state output latches which are transparent during the high level of the clock and latched during the low level of the clock. This device has a special feature which allows data to be passed through the RAM between the system and processor ports in either direction. This streaming is accomplished by latching in data from one port and asynchronously output enabling the other port. It is also possible to write to the RAM while streaming. Additional power supply pins have been utilized for maximum performance. The output buffer power (VCCQ) and ground pins (VSSQ) are electrically isolated from VSS and VCC, and supply power and ground only to the output buffers. This allows connecting the output buffers 3.3 V instead V if desired. 3.3 V output levels are chosen, the output buffer impedance in the ``high'' state is approximately equal to the impedance in the ``low'' state thereby allowing simplified transmission line terminations. The MCM62110 is available a 52­pin plastic leaded chip carrier (PLCC). This device is ideally suited for pipelined systems and systems with multiple data buses and multiprocessing systems, where a local processor has a bus isolated from a common system bus. Single ± 10% Power Supply Choice ± 10% Power Supplies for Output Level Compatibility Fast Access and Cycle Times: 15/17/20 ns Max Self­Timed Write Cycles Clock Controlled Output Latches Address, Chip Enable, and Data Input Registers Common Data Inputs and Data Outputs Dual I/O for Separate Processor and Memory Buses Separate Output Enable Controlled Three­State Outputs Odd Parity Checker During Reads Open Drain Output on Data Parity Error (DPE) Allowing Wire­ORing of Outputs High Output Drive Capability: 85 pF/Output at Rated Access Time High Board Density 52 Lead PLCC Package Active High and Low Chip Enables for Easy Memory Depth Expansion Can be used as Separate I/O x9

SIE PIE SOE POE W K VCC VSS DPE PDQ7 SDQ7 VSSQ PDQ5 SDQ5 VCCQ PDQ3 SDQ3 VSSQ A11 A10 VSS VCC A3 A1 PDQP SDQP VSSQ PDQ6 SDQ6 VCCQ PDQ2 SDQ2 VSSQ PDQ0 SDQ0

­ A14. Address Inputs K. Clock Input W. Write Enable E1. Active Low Chip Enable E2. Active High Chip Enable PIE. Processor Input Enable SIE. System Input Enable POE. Processor Output Enable SOE. System Output Enable DPE. Data Parity Error ­ PDQ7. Processor Data I/O PDQP. Processor Data Parity ­ SDQ7. System Data I/O SDQP. System Data Parity VCC. 5 V Power Supply VCCQ. Output Buffer Power Supply VSSQ. Output Buffer Ground VSS. Ground All power supply and ground pins must be connected for proper operation of the device. VCC VCCQ at all times including power up.

9 DATA LATCH CONTROL DATA REGISTER SOE ­ SDQ7, SDQP Output High­Z Data Out Data Out High­Z Data In Stream Data In Stream Data In High­Z Stream High­Z Data In Data In DPE Parity Out Parity Out Parity Out

PIE SIE POE X SOE X Mode Read N/A Write N/A Memory Subsystem Cycle Processor Read Copy Back Dual Bus Read NOP Processor Write Hit Allocate Write Through Allocate With Stream Cache Inhibit Write Cache Inhibit Read NOP Invalid ­ PDQ7, PDQP Output Data Out High­Z Data Out High­Z Data In High­Z Data In Stream Data In Stream Data High­Z Data In Data In Stream High­Z Notes

NOTES: A `0' represents an input voltage VIL and a `1' represents an input voltage VIH. All inputs must satisfy the specified setup and hold times for the falling or rising edge of K. Some entries in this truth table represent latched values. This table assumes that the chip is selected (i.e., = 0 and = 1) and VCC current is equal to ICCA. If this is not true, the chip will be in standby mode, the VCC current will equal or ISB2 DPE will default to 1 and all RAM outputs will be in High­Z. Other possible combinations of control inputs not covered by this note or the table above are not supported and the RAM's behavior is not specified. 2. If either IE signal is sampled low on the rising edge of clock, the corresponding is a don't care, and the corresponding outputs are High­Z. 3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM. 4. DPE is registered on the rising edge K at the beginning of the following clock cycle 5. No RAM cycle is performed. 6. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports ­ PDQ7 and PDQP ­ SDQ7 and SPDQ), and written into the RAM. 7. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other I/O port. 8. Data contention will occur.

NOTE: RAMP, RAM1. , refer to the data that is present on the RAMs internal bus, not necessarily data that resides in the RAM array. DPE is always delayed one clock, and is registered on the rising edge K at the beginning of the following clock cycle (see AC CHARACTERISTICS).

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = VSSQ 0 V)

Rating Power Supply Voltage Relative to VSS/VSSQ for Any Pin Except VCC and VCCQ Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC to +70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high­impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High­Z at power up.

Tstg 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.


 

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