Details, datasheet, quote on part number: MCM6209CJ15R2
Description64k X 4 Bit Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM6209CJ15R2 datasheet
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Features, Applications

The MCM6209C is fabricated using Motorola's high­performance silicon­gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual­in­line and plastic small­outline J­leaded packages. Single ± 10% Power Supply Fully Static No Clock or Timing Strobes Necessary Fast Access Times: and 35 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems Low Power Operation: 165 mA Maximum AC Fully TTL Compatible Three­State Output

­ A15. Address Input ­ DQ3. Data Input/Data Output W. Write Enable G. Output Enable E. Chip Enable NC. No Connection VCC. Power Supply 5 V) VSS. Ground

Mode Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA Output High­Z Dout High­Z Cycle Read Write

Rating Power Supply Voltage Relative to VSS For Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Value 0.5 to VCC + 70 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high­impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

Tstg 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.


Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min Typ 5.0 Max 5.5 VCC 0.3** 0.8 Unit V

* VIL (min) 0.5 V dc; VIL (min) V ac (pulse width 20 ns) VIH (max) = VCC 0.3 V dc; VIH (max) = VCC V ac (pulse width 20 ns)

Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (E = VIH G = VIH, Vout 0 to VCC) Standby Current (E VCC ­ 0.2 V*, Vin VSS V, or VCC 0.2 V, VCC = Max, = 0 MHz) Output Low Voltage (IOL = 8.0 mA) Output High Voltage (IOH ­ 4.0 mA) Symbol Ilkg(I) Ilkg(O) ISB2 VOL Min Max Unit mA V

VOH 2.4 *For devices with multiple chip enables, E1 and E2 are represented E in this data sheet. is of opposite polarity to E.

CAPACITANCE = 1 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic Address Input Capacitance Control Pin Input Capacitance (E, G, W) I/O Capacitance Symbol Cin CI/O Max 6 8 Unit pF

Input Timing Measurement Reference Level. 1.5 V Input Pulse Levels. 3.0 V Input Rise/Fall Time. 5 ns Output Timing Measurement Reference Level. 1.5 V Output Load. Figure 1A Unless Otherwise Noted

NOTES: W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 5. Transition is measured 500 mV from steady­state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G VIL).

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.


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