Details, datasheet, quote on part number: MCM56824AFN25AZP25
PartMCM56824AFN25AZP25
Category
Description8k X 24 Bit Fast Static RAM
CompanyMotorola Semiconductor Products
DatasheetDownload MCM56824AFN25AZP25 datasheet
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Features, Applications

The a 196,608 bit static random access memory organized as 8,192 words of 24 bits. The device integrates x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic. The availability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple devices are used. With either chip enable input unasserted, the device will enter standby mode, useful in low­power applications. A single on­chip multiplexer selects A12 or X/Y as the highest order address input depending upon the state of the V/S control input. This feature allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically re­partitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. By connecting A15 to the VECTOR/SCALAR (V/S) MUX control pin, such partitioning can occur with no additional components. This allows efficient utilization of the RAM resource irrespective of operand DQ0 type. See application diagrams at the end of this document for additionDQ1 al information. DQ2 Multiple power and ground pins have been utilized to minimize effects VSS induced by output noise. DQ3 The MCM56824A is available a 52 pin plastic leaded chip­carrier DQ4 (PLCC) and x 10 grid, 86 bump surface mount PBGA. DQ5 Single ± 10% Power Supply Fast Access and Cycle Times: 20/25/35 ns Max Fully Static Read and Write Operations Equal Address and Chip Enable Access Times Single Bit On­Chip Address Multiplexer Active High and Active Low Chip Enable Inputs Output Enable Controlled Three State Outputs High Board Density PLCC Package Low Power Standby Mode Fully TTL Compatible PIN NAMES

­ A11. Address Inputs A12, X/Y. Multiplexed Address V/S. Address Multiplexer Control W. Write Enable E1, E2. Chip Enable G. Output Enable ­ DQ23. Data Input/Output VCC. +5 V Power Supply VSS. Ground NC. No Connection For proper operation of the device, all VSS pins must be connected to ground. DQ7 DQ8 VSS DQ9 DQ10


E1 E2 V/S Mode Not Selected Not Selected Output Disable Read Using X/Y Read Using A12 Write Using X/Y Write Using A12 Supply Current ISB ICC I/O Status High­Z Data Out Data Out Data In Data In

Rating Power Supply Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value 0.5 to VCC + 125 Unit W °C This device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high­impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is assumed in a test socket or mounted on a printed circuit board with at least 300 LFPM of transverse air flow being maintained.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

(VCC + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS 0 V)

Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) V ac (pulse width 20 ns) Symbol VCC VIH VIL Min Typ 5.0 Max 5.5

Parameter Input Leakage Current (All Inputs, Vin 0 to VCC) Output Leakage Current (G = VIH, E1 = VIH, E2 = VIL, Vout 0 to VCC) AC Supply Current (G = VIH, E1 = VIL, E2 = VIH, Iout = 0 mA, All Other Inputs VIL 0.0 V and VIH V) MCM56824A­20 Cycle Time: ns MCM56824A­25 Cycle Time: ns MCM56824A­35 Cycle Time: 35 ns Standby Current (E1 = VIH, E2 = VIL, All Inputs = VIL or VIH) CMOS Standby Current (E1 VCC 0.2 V, All Inputs VCC 0.2 V) Output Low Voltage (IOL + 8.0 mA) Output High Voltage (IOH ­ 4.0 mA) Symbol Ilkg(i) Ilkg(O) ICCA ISB1 ISB2 VOL VOH mA V Min Max Unit µA mA

CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Input Capacitance Input/Output Capacitance All Pins Except ­ DQ23 Symbol Cin Cout Typ 4 6 Max 6 8 Unit pF


 

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