Details, datasheet, quote on part number: M5M4V64S20ATP-8
CategoryMemory => DRAM
Description64m ( 4-bank X 4194304-word X 4-bit ) Synchronous DRAM
CompanyMitsubishi Electronics America, Inc.
DatasheetDownload M5M4V64S20ATP-8 datasheet
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Features, Applications

Some of contents are subject to change without notice.

The x 4-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S20ATP achieves very high speed data rate to 125MHz, and is suitable for main memory or graphic memory in computer systems.

Vdd NC VddQ NC DQ0 VssQ NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS A2 A3 Vdd

- Single 3.3vą0.3v power supply - Clock frequency 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A9 - LVTTL Interface 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output

Memory Array Memory Array Memory Array Memory Array Bank #0 Bank #1 Bank #2 Bank #3
This rule is applied to only Synchronous DRAM family.

Cycle Time (min.) 12: 12ns Package Type TP: TSOP(II) Process Generation Function 0: Random Column, 1: 2N-rule Organization 4: x16 Synchronous DRAM Density 64:64M bits Interface S: SSTL, V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation

CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS /RAS, /CAS, /WE Input Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only.

Input / Output Input Power Supply Power Supply


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