Details, datasheet, quote on part number: GAL16LV8D
PartGAL16LV8D
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => SPLDs (Simple PLD)
DescriptionGAL16LV8C (3.3V)8 Macrocells
CompanyLattice Semiconductor Corp.
DatasheetDownload GAL16LV8D datasheet
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Features, Applications
Features

HIGH PERFORMANCE E2CMOS® TECHNOLOGY 3.5 ns Maximum Propagation Delay Fmax = 250 MHz 2.5 ns Maximum from Clock Input to Data Output UltraMOS® Advanced CMOS Technology 3.3V LOW VOLTAGE 16V8 ARCHITECTURE JEDEC-Compatible 3.3V Interface Standard 5V Compatible Inputs I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C) ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only) E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells 100% Tested/100% Yields High Speed Electrical Erasure (<100ms) 20 Year Data Retention EIGHT OUTPUT LOGIC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity PRELOAD AND POWER-ON RESET OF ALL REGISTERS 100% Functional Testability APPLICATIONS INCLUDE: Glue Logic for 3.3V Systems DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

The 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering GAL16LV8C-10LJ GAL16LV8C-15LJ Package 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC

GAL16LV8D Device Name GAL16LV8C Speed (ns) L = Low Power Grade Blank = Commercial

The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations a GAL16LV8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL16LV8 can emulate. It also shows the OLMC mode under which the GAL16LV8 emulates the PAL architecture.

PAL Architectures Emulated 16P2 GAL16LV8 Global OLMC Mode Registered Complex Simple

Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output.

Registered ABEL CUPL LOG/iC OrCAD-PLD PLDesigner TANGO-PLD P16V8R2 G16V8R

1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later.


 

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