|Category||Communication => Wireless => Commlink|
|Datasheet||Download ISL5239 datasheet
The ISL5239 Pre-Distortion Linearizer (PDP) is a full featured component for Power Amplifier (PA) linearization to improve PA power efficiency and reduce PA cost. The Radio Frequency (RF) PA is one of the most expensive and power-consuming devices in any wireless communication system. The ideal RF PA would have an entirely linear relationship between input and output, expressed as a simple gain which applies at all power levels. Unfortunately, realizable RF amplifiers are not completely linear and the use of pre-distortion techniques allows the substitution of lower cost/power PA's for higher cost/power PA's. The ISL5239 pre-distortion linearizer enables the linearization of less expensive PA's to provide more efficient operation closer to saturation. This provides the benefit of improved linearity and efficiency, while reducing PA cost and operational expense. The ISL5239 features a 125 MHz pre-distortion bandwidth capable of full 5th order intermodulation correction for signal bandwidths to 20 MHz. This bandwidth is particularly well suited for 3G cellular deployments of UMTS and CDMA2000. The device also corrects for PA memory effects that limit predistortion performance including self heating. The ISL5239 combines an input formatter and interpolator, pre-distortion linearizer, an IF converter, correction filter, gain/phase/offset adjustment, output formatter, and input and feedback capture memories into a single chip controlled a 16-bit linearizer interface. The ISL5239 supports log of power, linear magnitude, and linear power based pre-distortion, utilizing two Look-Up Table (LUT) based algorithms for the pre-distortion correction. The
device provides programmable scaling and offset correction, and provides for phase imbalance adjustment.Features
Output Sample Rates to 125MSPS Full 20 MHz Signal Bandwidth Dynamic Memory Effects Compensation Input and Feedback Capture Memories LUT-based Digital Pre-distortion Two 18-bit Output Busses with Programmable Bit-Width 16-Bit Parallel µProcessor Interface Input Interpolator x4, x8 Programmable Frequency Response Correction Low Power Architecture Threshold Comparator for Internal Triggering Quadrature or Digital IF Architecture Lowest-Cost Full-Featured Part AvailableApplications
Base Station Power Amplifier Linearization Operates with ISL5217 in Software Radio Solutions Compatible with the or ISL5929 D/A Converters
PART NUMBER ISL5239KI ISL5239EVAL1 TEMP RANGE ( oC) 85 25 PACKAGE 196 Ld BGA Evaluation Kit PKG. NO V196.15x15
SERCLK SERSYNC SEROUT SERIN INPUT FORMATTER AND INTERPOLATOR X4, X8 PRE-DISTORTER WITH TWO x 60 LUTs IF CONVERTER REAL 1X REAL 2X COMPLEX CORRECTION FILTER REAL 1X REAL 2X COMPLEX GAIN / PHASE OFFSET ADJUST OUTPUT DATA FORMATTER 8-18 BIT-WIDTH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved CommLinkTM is a trademark of Intersil Americas Inc.BYPASS CORRECTION FILTER REAL 1X REAL 2X COMPLEX
BYPASS GAIN / PHASE OFFSET ADJUST. OUTPUT DATA FORMATTER 8-18 BIT-WIDTH
HALF BAND BANDI / FILTER / Q IFIP I,Q I CM TEST Q
TEST FUNC. SEL. OFFSET SCALE PD MAG. LUT DATA I LUT DATA Q LUT DELTA DATA I LUT DELTA DATA Q ACTIVE LUT ADDR LUT ADDR AUTO INCR. PWR INTGR PER. PWR LOW PWR HIGH
HM, KM, LM, GM, DC OFFSETS OUTPUT WORD WIDTH SEL. OUTPUT VALUE TYPE COEF. DATA REAL PIPELINE SEL. COEF. ADDR. SERIAL INPUT EN. COEF. B SELECT
TRIGIN PD MAG. MAX MIN uP TRIG SEL IFIP I,Q PD I,Q PD MAG. INPUT SEL TRIG INPUT DELAY COUNT uP INPUT STATE FB STATE THRESHOLD COMPARECOEF. A COEF. B SERIAL TO PAR. POWER INTEGRATOR
INPUT CAPTURE MEMORY 2K CM TEST I,Q MEMORY SELECT
NC B ISTRB P0 F VCCIO P10 J CLK P13 L DCTEST QIN16 N TRST P NC VCCC IOUT15 IOUT14 VCCIO GND IOUT6 IOUT5 VCCC QIN14 QIN10 VCCC IOUT10 IOUT8 GND VCCIO QIN4 IOUT16 GND IOUT7 VCCIO IOUT0 IOUT2 FBCLK TDI TMS QIN9 QIN2 VCCIO IOUT13 IOUT9 VCCC IOUT4 FB1 TRIGIN FB2 TDO TCK BUSY QIN6 QIN0 VCCC GND IOUT11 GND FB0 VCCC FB3 FB4 GND RESET P14 P15 TRIGOUT P6 P5 GND P11 SEROUT FB12 FB11 SERIN FB16 FB15 GND FB10 VCCC WR IIN5 GND VCCC FB19 FB18 VCCC QOUT16 QOUT12 VCCC IIN17 IIN14 VCCC IIN7 IIN3 VCCIO QOUT4 NC GND VCCC IIN0 QOUT15 GND QOUT11 GND VCCIO VCCC NC
NAME POWER SUPPLY VCCC VCCIO GND CLK RESET P<15:0> I I/O Positive Device Core Power Supply Voltage, 1.8V ±0.18V. Positive Device Input/Output Power Supply Voltage, 3.3V ±0.165V. Common Ground, 0V Input Clock. Rising edge drives all of the devices synchronous operations, except feedback capture. Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, reset all internal states, and halt all processing. 16-bit bi-directional data bus that operates with A<5:0>, CS, RD, and WR to write to and read from the devices internal control registers. When the host system asserts CS and RD simultaneously, is an output bus, under all other conditions, is an input bus. Bit 15 is the MSB. TYPE DESCRIPTION
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