|Category||Interface and Interconnect => Multi-Ports|
|Description||64K X 9 Sync, Dual-port RAM, Piplelined/flow-through|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 709189 datasheet
|Cross ref.||Similar parts: 709289|
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 7.5/9/12ns (max.) Low-power operation IDT709189L Active: 1.2W (typ.) Standby: 2.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
Full synchronous operation on both ports 4ns setup to clock and 0ns hold on all control, data, and address inputs Data input, address, and control registers Fast 7.5ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 12ns cycle time, 83MHz operation in Pipelined output mode TTL- compatible, single 5V (±10%) power supply Industrial temperature range +85°C) is available for selected speeds Available a 100-pin Thin Quad Flatpack (TQFP) packageA15L A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg.
The is a high-speed x 9 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT709189 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 1.2W of power.A1L A0L CNTENL CLKL ADSL GND ADSR CLKR CNTENR A5R A6R
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Left Port CE0L, CE1L R/WL OEL - I/O8L CLK L ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER - I/O8R CLKR ADSR CNTENR CNTRSTR FT/PIPER VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Clock Address Strobe Counter Enable Counter Reset Flow-Through/Pipeline Power Ground
OE CLK CE0 CE1 R/W I/O0-8 High-Z DATAIN DATAOUT High-Z Deselected--Power Down Deselected--Power Down Write Read Outputs Disabled
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST is an asynchronous input signal.Address An X Previous Address X Ap Addr Used 1 CLK(3) ADS L(4) H CNTEN
Mode Counter Reset to Address 0 External Address Utilized External Address Blocked --Counter Disabled Counter Enable--Internal Address Generation
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0 and 1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
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