Details, datasheet, quote on part number: 70824
Part70824
CategoryInterface and Interconnect => Multi-Ports
TitleMulti-Ports
Description4K X 16 Saramtm (Sequential Access / Random Access Memory)
CompanyIntegrated Device Technology, Inc.
DatasheetDownload 70824 datasheet
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Features, Applications
HIGH SPEED X 16 BIT) IDT70824S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAMTM)
Features

High-speed access ­ Military: 35/45ns (max.) ­ Commercial: 20/25/35/45ns (max.) Low-power operation ­ IDT70824S Active: 775mW (typ.) Standby: 5mW (typ.) ­ IDT70824L Active: 775mW (typ.) Standby: 1mW (typ.) x 16 Sequential Access Random Access Memory (SARAMTM) ­ Sequential Access from one port and standard Random Access from the other port ­ Separate upper-byte and lower-byte control of the Random Access Port High speed operation ­ 20ns tAA for random access port ­ 20ns tCD for sequential port ­ 25ns clock cycle time Architecture based on Dual-Port RAM cells

Compatible with Intel BMIC and 82430 PCI Set Width and Depth Expandable Sequential side ­ Address based flags for buffer control ­ Pointer logic supports up to two internal buffers Battery backup operation - 2V data retention TTL-compatible, single 5V (+10%) power supply Available in 80-pin TQFP and 84-pin PGA Military product compliant to MIL-PRF-38535 QML Industrial temperature range +85°C) is available for selected speeds

Description

The is a high-speed x 16-Bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter se-

Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer #2 End Address for Buffer #2 Flow Control Buffer Flag Status

IDT70824S/L High-Speed x 16 Sequential Access Random Access Memory

quencing for the sequential (synchronous) access port. Fabricated using CMOS high-performance technology, this memory device typically operates on less than 775mW of power at maximum highspeed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70824 is packaged a 80-pin Thin Quad Flatpack (TQFP) or 84-pin Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.



NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PN80-1 package body is approximately 1.4mm. G84-3 package body is approximately in x.16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.

IDT70824S/L High-Speed x 16 Sequential Access Random Access Memory

SYMBOL I/O0-I/O15 CE NAME Address Lines Inputs/Outputs Chip Enable I/O I DESCRIPTION Address inputs to access the 4096-word (16-Bit) memory array. Random access data inputs/outputs for 16-Bit wide data. When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port CE and CMD may not be LOW at the same time. When CMD is LOW, address lines A 0-A2, R/W, and inputs and outputs I/O0-I/O12, are used to access the control register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the same time. CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. When OE is LOW and W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in the High-impedance state. When LB is LOW, I/O0-I/O7 are accessible for re ad and write operations. When LB is HIGH, I/O0-I/O7 are tristated and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and is asynchronous from LB. Seven +5 power supply pins. All V CC pins must be connected to the same V CC supply. Ten ground pins. All ground pins must be connected to the same ground supply.

Output Enable Lower Byte, Upper Byte Enables

SYMBOL SI/O0-15 SCLK SCE NAME Inputs/Outputs Clock Chip Enable I/O I DESCRIPTION Sequential data inputs/outputs for 16-bit wide data. SI/O0-SI/O15,SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential access port address pointer increments 1 on each LOW-TO-HIGH transition of SCLK when CNTEN is LOW. When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transitio n of SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the High-impedance state. All data is retained , unless altered by the random access port. When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is independent of CE. When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/ W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination f a write cycle is done on the LOW-to -HIGH transition of SCLK if SR/W or SCE is HIGH. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the datain register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. When SSTRT2 is LOW, the start of address register #2 is loaded into the address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. EOB2 is output low when the address pointer is incremented to match the address stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or by writing ze ro into Bit 0 and/or Bit 1 of the control registe r at address 101. EOB1 and EOB2 are dependent on separate internal registers, and therefore separate match addresses. SOE controls the data outputs and is independe nt of SCLK. When SOE is LOW, output buffers and the se quentially ad dressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state. SOE is asynchronous to SCLK. When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.

Load Start of Address Register End of Buffer Flag
NOTE : 1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.

 

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