|Category||Interface and Interconnect => Multi-Ports|
|Description||32K X 16 Asynchronous Bank-switchable Dual-port SRAM|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 707278 datasheet
|Cross ref.||Similar parts: 7027|
|HIGH-SPEED x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
x 16 Bank-Switchable Dual-Ported SRAM Architecture Four independent x 16 banks 512 Kilobit of memory on chip Fast asynchronous address-to-data access time: 15ns User-controlled input pins included for bank selects Independent port controls with asynchronous address & data busses Four 16-bit mailboxes available to each port for interprocessor communications; interrupt option
Interrupt flags with programmable masking Dual Chip Enables allow for depth expansion without external logic UB and LB are available for or x16 bus matching TTL-compatible, single 5V (±10%) power supply Available a 100-pin Thin Quad Flatpack x 14mm)
MUX R/WL CE0L CE1L UBL LBL OEL 8Kx16 MEMORY ARRAY (BANK 0) MUX I/O8L-15L I/O0L-7L I/O CONTROL MUX 8Kx16 MEMORY ARRAY (BANK 1) MUX I/O CONTROL I/O8R-15R I/O0R-7R R/WR CE0R CE1R UBR LBR OER
BANK SELECT A5L(1) A0L(1) LBL/UBL OEL R/WL CEL MAILBOX INTERRUPT LOGIC A5R(1) A0R(1) LBR/UBR OER R/WR CER
NOTES: 1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.x 16 Bank-Switchable Dual-Ported SRAM with External Bank Selects
The is a high-speed 16 (512K bit) Bank-Switchable Dual-Ported SRAM organized into four independent x 16 banks. The device has two independent ports with separate controls, addresses, and I/O pins for each port, allowing each port to asynchronously access any x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow inter-processor communications. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707278 offers a maximum address-to-data access time as fast as 15ns, and is packaged a 100-pin Thin Quad Flatpack (TQFP). IV). Once a bank is assigned to a particular port, the port has full access to read and write within that bank. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The IDT707278 provides mailboxes to allow inter-processor communications. Each port has four 16-bit mailbox registers available to which it can write and read and which the opposite port can read only. These mailboxes are external to the common SRAM array, and are accessed by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an associated interrupt: a port can generate an interrupt to the opposite port by writing to the upper byte of any one of its four 16-bit mailboxes. The interrupted port can clear the interrupt by reading the upper byte. This read will not alter the contents of the mailbox. If desired, any source of interrupt can be independently masked via software. Two registers are provided to permit interpretation of interrupts: the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to. The information in this register provides post-mask signals: Interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. Truth Table V gives a detailed explanation of the use of these registers.
The is a high-speed asynchronous x 16 BankSwitchable Dual-Ported SRAM, organized in four x 16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array. There are four user-controlled Bank Select input pins, and each of these pins is associated with a specific bank within the memory array. Access to a specific bank is gained by placing the associated Bank Select pin in the appropriate state: VIH assigns the bank to the left port, and VIL assigns the bank to the right port (See Truth Tablex 16 Bank-Switchable Dual-Ported SRAM with External Bank Selects
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Address Inputs Bank Address Inputs Mailbox Access Control Gate Bank Select Inputs Read/Write Enable Output Enable Chip Enables I/O Byte EnablesBidirectional Data Input/Output Interrupt Flag (Output)(3) +5VPower Ground
NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table IV for more details. When changing the bank assignments, accesses of the affected banks must be suspended. Accesses may continue uninterrupted in banks that are not being reallocated. 3. Generated upon mailbox access. 4. All Vcc pins must be connected to power supply. 5. All GND pins must be connected to ground supply. 6. The first six address pins (A0-A5) for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs (A6-A12 ignored).
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