|Category||Interface and Interconnect => Multi-Ports|
|Description||16K X 16 Dual-port RAM W/int|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 70261 datasheet
|Cross ref.||Similar parts: 70261A, CY7C026A, QS70261|
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access Commercial: 15/20/25/35/55ns (max.) Industrial 20/25/35/55ns (max.) Low-power operation IDT70261S Active: 750mW (typ.) Standby: 5mW (typ.) IDT70261L Active: 750mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility
IDT70261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 100-pin Thin Quad Flatpack Industrial temperature range +85OC) is available for selected speeds
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull.Description
The is a high-speed x 16 Dual-Port Static RAM. The IDT70261 is designed to be used as a stand-alone Dual-Port RAM as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach 32bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT70261 is packaged a 100-pin TQFP.
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Left Port Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power GroundSymbol VCC GND V IL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min.
1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
I/O8-15 High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z
Mode Deselected: Power-Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
Mode Read Data in Semaphore Flag Read Data in Semaphore Flag Write I/O0 into Semaphore Flag Write I/O0 into Semaphore Flag Not Allowed Not Allowed
NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all - I/O15 These eight semaphores are addressed A 2.
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