|Category||Interface and Interconnect => Multi-Ports|
|Description||64K x9 Dual-port RAM|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 7018 datasheet
|Cross ref.||Similar parts: 7019|
True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20ns (max.) Low-power operation IDT7018L Active: 1W (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic IDT7018 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device
M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available a 100-pin TQFP Industrial temperature range +85°C) is available for selected speeds
NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).Description
The is a high-speed x 9 Dual-Port Static RAM. The IDT7018 is designed to be used as a stand-alone 576K-bit Dual-Port RAM as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach 18-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 1W of power. The IDT7018 is packaged a 100-pin Thin Quad Flatpack (TQFP).
NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking.
Left Port CE0L, CE1L R/WL OEL - I/O8L SEML INTL BUSYL Right Port CE0R, CE1R R/WR OER - I/O8R SEMR INTR BUSYR M/S VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial to +7.0 Military to +7.0 Unit VSymbol VCC Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. Typ. 5.0 0
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited < 20mA for the period of VTERM > Vcc + 10%.NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
Parameter(1) Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 3V or from to 0V.
NOTES: 1. Industrial Temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature.
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