Details, datasheet, quote on part number: W49V002AQ
PartW49V002AQ
CategoryMemory => Flash
Description256Kx8
CompanyInformation Storage Devices, Inc
DatasheetDownload W49V002AQ datasheet
  

 

Features, Applications
Preliminary x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

GENERAL DESCRIPTION The a 2 -megabit, 3.3-volt only CMOS flash memory organized × 8 bits. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49V002A results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification 1.0. The device can also be programmed and erased using standard EPROM programmers.

FEATURES
- Active current: 25 mA (typ.) - Standby current: 20 ľA (typ.)

Automatic program and erase timing with internal VPP generation End of program or erase detection

Fast Erase operation: 150 mS (typ.) Endurance: 10K cycles (typ.) Twenty-year data retention Hardware data protection

Latched address and data TTL compatible I/O Available packages: 32L PLCC and 32L
Two 8K bytes Parameter Blocks Four Main Memory Blocks (with 32K bytes, 64K

Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Address/Data Inputs LPC Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable

Power Supply Ground Reserve Pins No Connection

#WP #TBL CLK LAD[3:0] #LFRAM MODE #INIT #RESET MAIN MEMORY BLOCK1 32K BYTES R/#C A[10:0] DQ[7:0] #OE #WE Programmer Interface MAIN MEMORY BLOCK2 64K BYTES MAIN MEMORY BLOCK3 64K BYTES MAIN MEMORY BLOCK4 64K BYTES LPC Interface BOOT BLOCK 16K BYTES PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES 30000 2FFFF

This device can be operated in two interface modes, one is Programmer interface mode, the other is LPC interface mode. The MODE pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When MODE pin is set to high state, the device is in the Programmer mode; while the MODE pin is set to low state(or leaved no connection), is in the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go through the address inputs A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through LAD[3:0] to communicate with the system chipset.

In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As in the LPC interface mode, the read or write is determined by the "bit 1 of CYCLE TYPER+DIR".

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

The seven sectors, one boot block and two parameter blocks and four main blocks, can be erased individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

The W49V002A is programmed on a byte-by-byte basis. Program operation can only change logical data Publication Release Date: April 2001 Revision A1


 

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