|Category||ASICs => Gate Array|
|Description||0.6m/0.5m CMOS Fast-turn Gate Array Product Family|
|Company||Chip Express Corporation|
|Datasheet||Download CX2001 datasheet
The CX2000, 0.6um Advanced Gate Array product family features density ranges from to 100K usable gates, to 96K bits of configurable embedded RAM / ROM, and to 556 I/Os. Using Chip Express' proprietary architecture, fast-turn delivery of prototypes and production is achieved. Seamless transitions from prototypes through volume production permit scalable inventory management.
Advanced Gate Array architecture Low NRE and start-up costs Fast time to production 0.6um CMOS TLM process or 5V operation with mixed mode I/O 5V tolerance with reference voltage PCI compliant outputs / 5V) Power dissipation: 2.6µW / MHz / Gate 1.1µW / MHz / Gate 3.3V 800 MHz maximum flip-flop toggle rate Analog PLL operating frequency to 250 MHz Embedded memory: Configurable as single-port RAM, dual-port RAM or ROM to 96k bits / 24 individual memory configurations Worst-case performance: 200 MHz 5V; 150 MHz @ 3.3V Fully static, synchronous RAM Word depth: programmable to 4096 bits Word width: programmable 1-64 bits
Available masterslices in the CX2000 product family are shown in Table 1. TABLE 1. CX2000 MASTERSLICES BASE ARRAY CX2121 CX2201 USABLE ASIC GATES (K) EMBEDDED MEMORY (K BITS) MAX MEMORY INSTANTIATIONS APLL MAX I/O
Note: Each memory block can be used as one dual-port memory or two single-port memories. Max I/O include both signals and power / ground.
Synopsys DC and Design Ware support Low power flip-flops Built-in scan MUX in flip-flops 26 simple gates; 36 complex gates 31 flip-flops 24 latches Multiplexers, decoders Tristate / drive cells 1280 input / output cells
All I/O cells are programmable as VDD, VSS, input, output, or bi-directional. This flexibility allows the user to properly ratio power pins with output drive requirements or match specific pin-out when replacing existing devices.
The CX2000 library contains a large selection of input, output, and bi-directional cells that accommodate a wide range of designs. Input cells can be personalized with internal pull-up or pull-down resistors and with or without hysteresis. Output cells include slew rate control, current drive capability from 12mA, as well as N channel and P channel open drains. If required, outputs can be used in parallel to enable increased drive capability. Each I/O can be programmed independently for or 5V.
Tables 2, 3, and 4 provide data related to absolute maximum ratings, recommended operating conditions, and DC characteristics over operating conditions. TABLE 2. ABSOLUTE MAXIMUM RATINGS SYMBOL VDD VDDIO (3.3V) VDDIO (5V) VIN TJ TSTG TSOL DESCRIPTION Supply voltage I/O supply voltage I/O supply voltage DC input voltage range Junction temperature Storage temperature Soldering lead temperature (10 seconds) MIN -0.3 0 VSS -0.3 --65 -MAX 4.6 5.5 VDDWELL UNITS °C
TABLE 3. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD Supply voltage (3.3V) DESCRIPTION Commercial TJ 100°C) Industrial TJ 115°C) Military TJ 125°C) Commercial TJ 100°C) Supply voltage Industrial 115°C) (5V) Military TJ 125°C) TTL inputs Input high voltage CMOS inputs TTL inputs Input low voltage CMOS inputs Input signal transition time MIN VDD 0 -MAX VDD 0.8 0.3 VDD 10 UNITS nS
TABLE 4. DC CHARACTERISTICS OVER OPERATING CONDITIONS SYMBOL VOH VOL IIN Output high voltage Output low voltage Input leakage current Input capacitance QFP packages BGA packages DESCRIPTION TTL outputs CMOS outputs TTL outputs CMOS outputs MIN 2.45 0.7 VDD ---10 --MAX --0.45 0.3 VDD 10 --UNITS µA Refer to website
Chip Express spends considerable development effort to ensure that taping out a design to an Advanced Gate Array ASIC is a simple, painless and, risk-free endeavor. Chip Express provides an on-line downloadable design kit in both Verilog and VHDL with complete libraries and a design-flow script which leads users through the development process in a logical, linear fashion, ensuring trouble-free product development every time. The Chip Express Design Toolkit checks design constraints, I/O rules, typical, min and max case timing, glitches, contention and handoff database completeness. Chip Express' standard ASIC and FPGA design flows are shown on the next page.
An increasing number of customers prefer to handoff their RTL designs early and let Chip Express perform the entire timing closure loop, including synthesis and final simulations. Chip Express can also convert obsolete design netlists, FPGA bitmaps, and even well-specified concept designs into prototypes rapidly and reliably.
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