Details, datasheet, quote on part number: JTS83102G0-1V1B
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 10 bit
Description10-bit 2 GSPS ADC<<<>>>this State-of-the-art 10-bit 2 GSPS Converter Offers an Unprecedented Bandwidth of 3.3 GHZ And Excellent Band Flatness, Allowing to Directly Digitize Very High if Signals (2nd And 3rd Nyquist Zones) With High Linearity : The SFDR Remains in The -55 DBFS Range at 2 GSPS / 2 GHZ Input Frequency. Along With Atmel TS81102G0 Demultiplexer it is The Perfect Solution For Upgrading Radars, Wide-band Receivers or High-end Instrumentation Systems.
CompanyATMEL Corporation
DatasheetDownload JTS83102G0-1V1B datasheet
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Features, Applications

to 2 Gsps Sampling Rate Power Consumption: 4.6W 500 mVpp Differential 100 or Single-ended 50 (±2 Analog Inputs Differential 100 or Single-ended 50 Clock Inputs ECL or LVDS Output Compatibility 50 Differential Outputs with Common Mode not Dependent on Temperature ADC Gain Adjust Sampling Delay Adjust Offset Control Capability Data Ready Output with Asynchronous Reset Out-of-range Output Bit Selectable Decimation by 32 Functions Gray or Binary Selectable Output Data; NRZ Output Mode Pattern Generator Output (for Acquisition System Monitoring) Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected) CBGA 152 Cavity Down Hermetic Package CBGA Package Evaluation Board TSEV83102G0BGL Companion Device: DMUX 1:4/1:8 2 Gsps TS81102G0

3.3 GHz Full Power Input Bandwidth (-3 dB) Gain Flatness: 0.2 dB (from to 1.5 GHz) Low Input VSWR: 1.2 Max from to 2.5 GHz SFDR = -59 dBc; 7.6 Effective Bits = 1.4 Gsps, FIN = 700 MHz [-1 dBFS] SFDR = -53 dBc; 7.1 Effective Bits = 1.4 Gsps, FIN = 1950 MHz [-1 dBFS] SFDR = -54 dBc; 6.5 Effective Bits = 2 Gsps, FIN = 2 GHz [-1 dBFS] Low Bit Error Rate at 2 Gsps


Direct RF Down Conversion Wide Band Satellite Receiver High-speed Instrumentation High-speed Acquisition Systems High-energy Physics Automatic Test Equipment Radar

Temperature Range for Packaged Device: ­ "C" grade: C < Tc; C ­ "V" grade: C < Tc; 110° C Standard Die Flow (upon Request)


The is a monolithic 10-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates to 2 Gsps. It uses an innovative architecture, including an on-chip Sample and Hold (S/H). The 3.3 GHz full power input bandwidth and band flatness performances enable the digitizing of high IF and large bandwidth signals.

The 10-bit 2 Gsps ADC. The device includes a front-end master/slave Track and Hold stage (Sample and Hold), followed by an analog encoding stage (Analog Quantizer), which outputs analog residues resulting from analog quantization. Successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuit and resynchronization stage, followed by 50 differential output buffers. The TS83102G0B works in a fully differential mode from analog inputs to digital outputs. A differential Data Ready output (DR/DRB) is available to indicate when the outputs are valid and an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the first acquisition. The control pin B/GB (A11 of the CBGA package) is provided to select either a binary or gray data output format. The gain control pin (R9 of the CBGA package) is provided to adjust the ADC gain transfer function. A Sampling Delay Adjust function (SDA) may be used to ease the interleaving of ADCs. A pattern generator is integrated on the chip for debug or acquisition setup. This function is activated through the PGEB pin (A9 of the CBGA package). An Out-of-range bit (OR/ORB) indicates when the input overrides 0.5 Vpp. A selectable decimation by 32 functions is also available for enhanced testability coverage (A10 of the CBGA package), along with the die junction temperature monitoring function. The TS83102G0B uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allows enhanced radiation tolerance (over 100 kRad (Si) total dose expected tolerance).


Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VIN and VINB Clock input voltage Maximum difference between VCLK and VCLKB Static input voltage Digital input voltage Digital output voltage Junction temperature Note: Symbol VCC DVEE VPLUSD VEE DVEE to VEE VIN or VINB VIN - VINB VCLK or VCLKB VCLK - VCLKB VO TJ GA, SDA SDAEN, DRRB, B/GB, PGEB, DECB Comments Value GND to 6.0 GND to -5.7 GND to 2.5 GND to 0.8 VPLUSD min operating -2.2 to VPLUSD max operating 0.8 130 Unit Vpp V °C

Absolute maximum ratings are short term limiting values (referenced to GND to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.

Parameter Positive supply voltage Symbol VCC Differential ECL output compatibility Positive digital supply voltage VPLUSD LVDS output compatibility Comments Min Grounded Maximum operating VPLUSD Negative supply voltages Differential analog input voltage (full-scale) Clock input power level (ground common mode) VEE, DVEE VIN, VINB VIN - VINB PCLK, PCLKB 50 differential or single-ended 50 single-ended clock input or 100 differential clock (recommended)


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