Details, datasheet, quote on part number: A42U2604V-60
PartA42U2604V-60
CategoryMemory => DRAM
DescriptionDRAM Sdram Sgram 16Mb x4
CompanyAMIC Technology Corporation
DatasheetDownload A42U2604V-60 datasheet
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Features, Applications
Document Title X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History
Initial issue Modify symbol HE dimensions in TSOP 24L package information Modify AC. and DC. data
Features

n Organization: 4,194,304 words X 4 bits n Part Identification A42U2604 (2K Ref.) n Single 2.5V power supply/built-in VBB generator n Low power consumption - Operating: 75mA (-50 max) - Standby: 1mA (TTL), 1mA (CMOS), 350A (Self-refresh current) n High speed 50/60/80 ns RAS access time 22/27/37 ns column address access time 13/15/20 ns CAS access time 20/24/32 ns EDO Page Mode Cycle Time n Industrial operating temperature range: to +85C for -U n Fast Page Mode with Extended Data Out n 2K Refresh Cycle 32ms n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages 300mil, 24/26-pin SOJ 300mil, 24/26-pin TSOP type II package

The is a new generation randomly accessed memory for graphics, organized by 4-bit configuration. This product can execute Write and Read operation via CAS pin. The A42U2604 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). This allow random access to 2048(2K Ref.) words within a row a 50/42/31 MHz EDO cycle, making the A42U2604 ideally suited for graphics, digital signal processing and high performance computing systems.

Description Address Inputs (2K product) Data Input/Output Row Address Strobe Column Address Strobe Write Enable Output Enable 2.5V Power Supply Ground No Connection

Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time Unit ns

The A42U2604 reads and writes data by multiplexing an 22-bit address into a 11-bit(2K) row and column address. RAS and CAS are used to strobe the row address and the column address, respectively. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge WE or CAS , whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with RAS , CAS ,

valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller.

EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS. While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42U2604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain

The initial application of the VCC supply requires 200 s wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.


 

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