Details, datasheet, quote on part number: AM29F040B-120
PartAM29F040B-120
CategoryMemory => Flash => Parallel Flash => 4M
Title4M
Description4 Megabit CMOS 5.0 Volt-only, Sector Erase Flash Memory: 512kx8
CompanyAdvanced Micro Systems, Inc.
DatasheetDownload AM29F040B-120 datasheet
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Features, Applications
4 Megabit x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

10% for read and write operations Minimizes system level power requirements s Manufactured 0.32 m process technology Compatible with m Am29F040 device s High performance Access times as fast ns s Low power consumption 20 mA typical active read current 30 mA typical program/erase current 1 A typical standby current (standard access time to active mode) s Flexible sector architecture 8 uniform sectors of 64 Kbytes each Any combination of sectors can be erased Supports full chip erase Sector protection: A hardware method of locking sectors to prevent any program or erase operations within that sector s Embedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s 20-year data retention at 125C Reliable operation for the life of the system s Package options 32-pin PLCC, TSOP, or PDIP s Compatible with JEDEC standards Pinout and software compatible with single-power-supply Flash standard Superior inadvertent write protection s Data# Polling and toggle bits Provides a software method of detecting program or erase cycle completion s Erase Suspend/Erase Resume Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation

This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

The a 4 Mbit, 5.0 volt-only Flash memory organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of data are divided into eight sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0DQ7. The Am29F040B is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD's 0.32 m process technology, and offers all the features and benefits of the Am29F040, which was manufactured using 0.5 m process technology. In addtion, the Am29F040B has a second toggle bit, DQ2, and also offers the ability to program in the Erase Suspend mode. The standard Am29F040B offers access times of and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

Product Selector Guide. Block Diagram. Connection Diagrams. Pin Configuration. Logic Symbol. Ordering Information. Device Bus Operations. Requirements for Reading Array Data..................................... Writing Commands/Command Sequences.............................. Program and Erase Operation Status...................................... Standby Mode.......................................................................... Output Disable Mode................................................................ Absolute Maximum Ratings. 19

Figure 5. Maximum Negative Overshoot Waveform..................... 19 Figure 6. Maximum Positive Overshoot Waveform....................... 19

Operating Ranges. 19 DC Characteristics. 20 TTL/NMOS Compatible.......................................................... 20 CMOS Compatible.................................................................. 20 Test Conditions. 21

Figure 7. Test Setup..................................................................... 21 Table 6. Test Specifications........................................................... 21

Key to Switching Waveforms. 21 AC Characteristics. 22 Read Only Operations............................................................ 22

Figure 9. Program Operation Timings........................................... Figure 10. Chip/Sector Erase Operation Timings......................... Figure 11. Data# Polling Timings (During Embedded Algorithms) Figure 12. Toggle Bit Timings (During Embedded Algorithms)..... Figure 13. DQ2 vs. DQ6................................................................

Low VCC Write Inhibit...................................................................... 10 Write Pulse "Glitch" Protection........................................................ 10 Logical Inhibit.................................................................................. 10 Power-Up Write Inhibit.................................................................... 10

Alternate CE# Controlled Writes.................................................... 27 Figure 14. Alternate CE# Controlled Write Operation Timings..... 28

Command Definitions. 11 Reading Array Data................................................................ 11 Reset Command..................................................................... 11 Autoselect Command Sequence............................................ 11 Byte Program Command Sequence....................................... 11

Chip Erase Command Sequence........................................... 12 Sector Erase Command Sequence........................................ 12 Erase Suspend/Erase Resume Commands........................... 13

DQ6: Toggle Bit I.................................................................... DQ2: Toggle Bit II................................................................... Reading Toggle Bits DQ6/DQ2.............................................. DQ5: Exceeded Timing Limits................................................ DQ3: Sector Erase Timer.......................................................

Figure 4. Toggle Bit Algorithm........................................................ 17 Table 5. Write Operation Status.......................................................18

Erase and Programming Performance. 29 Latchup Characteristics. 29 TSOP Pin Capacitance. 29 PLCC and PDIP Pin Capacitance. 30 Data Retention. 30 Physical Dimensions. PD 032--32-Pin Plastic DIP................................................... PL 032--32-Pin Plastic Leaded Chip Carrier......................... TS 032--32-Pin Standard Thin Small Package...................... 33 TSR032--32-Pin Reversed Thin Small Outline Package....... 34 Revision Summary. 35 Revision A (May 1997)........................................................... 35 Revision B (January 1998)..................................................... 35 Revision B+1 (January 1998)................................................. 35 Revision B+2 (April 1998)....................................................... 35 Revision C (January 1999)..................................................... 35 Revision C+1 (February 1999)............................................... 35 Revision C+2 (May 1999)................................................. 35 Revision D (November 1999)........................................... 35 Revision E (November 2000)............................................ 35


 

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