Details, datasheet, quote on part number: AX500-CS896
DescriptionAxcelerator Family Fpgas
CompanyActel Corporation
DatasheetDownload AX500-CS896 datasheet


Features, Applications

350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os to 2 Million Equivalent System Gates to 684 I/Os to 10,752 Dedicated Flip-Flops to 295 kbits Embedded SRAM/FIFO Manufactured on Advanced 0.15 m CMOS Antifuse Process Technology, 7 Layers of Metal Single-Chip, Nonvolatile Solution to 100% Resource Utilization with 100% Pin Locking 1.5V Core Voltage for Low Power Footprint Compatible Packaging Flexible, Multi-Standard I/Os: 2.5V, 3.3V Mixed Voltage Operation Bank-Selectable I/Os 8 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3V PCI-X Differential I/O Standards: LVPECL and LVDS


Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 Registered I/Os Hot-Swap Compliant I/Os (except PCI) Programmable Slew Rate and Drive Strength on Outputs Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory: Variable-Aspect 4,608-bit RAM Blocks x18, x36 Organizations Available) Independent, Width-Configurable Read and Write Ports Programmable Embedded FIFO Control Logic Segmentable Clock Resources Embedded Phase-Locked Loop: 14-200 MHz Input Range Frequency Synthesis Capabilities to 1 GHz Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Actel Silicon Explorer II Boundary-Scan Testing Compliant with IEEE Standard 1149.1 (JTAG) FuseLock TM Secure Programming Technology Prevents Reverse Engineering and Design Theft

Table 1-1 Axcelerator Family Product Profile Device Capacity (in Equivalent System Gates) Typical Gates Modules Register (R-cells) Combinatorial (C-cells) Maximum Flip-Flops Embedded RAM/FIFO Number of Core RAM Blocks Total Bits of Core RAM Clocks (Segmentable) Hardwired Routed PLLs I/Os I/O Banks Maximum User I/Os Maximum LVDS Channels Total I/O Registers Package CSP PQFP BGA FBGA CQFP CCGA

i *See Actel's website for the latest version of the datasheet.

896 I Application Blank = Commercial PP = Pre-Production I = Industrial M = Military = MIL-STD-883 Class B Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant Packaging Package Type BG = Ball Grid Array (1.27mm pitch) FG = Fine Ball Grid Array (1.0mm pitch) CS = Chip Scale Package (0.8mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) CQ = Ceramic Quad Flat Pack (0.5mm pitch) CG = Ceramic Column Grid Array Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard Part Number = 125,000 Equivalent System Gates = 250,000 Equivalent System Gates = 500,000 Equivalent System Gates = 1,000,000 Equivalent System Gates = 2,000,000 Equivalent System Gates

Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint compatible with one another.

Package FG896 FG1152 Notes: C = Commercial I = Industrial M = Military = MIL-STD-883 Class I, M

Refer to the following documents located on the Actel website for additional packaging information. Package Mechanical Drawings Package Thermal Characteristics and Weights Hermatic Package Mechanical Information Contact your local Actel representative for device availability.


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