|Datasheet||Download MC145480D datasheet
The is a general purpose per channel PCM CodecFilter with pin selectable MuLaw or ALaw companding, and is offered in 20pin DIP, SOG, and SSOP packages. This device performs the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems. This device is designed to operate in both synchronous and asynchronous applications and contains an onchip precision reference voltage. This device has an input operational amplifier whose output is the input to the encoder section. The encoder section immediately lowpass filters the analog signal with an active RC filter to eliminate very high frequency noise from being modulated down to the passband by the switched capacitor filter. From the active RC filter, the analog signal is converted to a differential signal. From this point, all analog signal processing is done differentially. This allows processing of an analog signal that is twice the amplitude allowed by a singleended design, which reduces the significance of noise to both the inverted and noninverted signal paths. Another advantage of this differential design is that noise injected via the power supplies is a commonmode signal that is cancelled when the inverted and noninverted signals are recombined. This dramatically improves the power supply rejection ratio. After the differential converter, a differential switched capacitor filter band passes the analog signal from 3400 Hz before the signal is digitized by the differential compressing A/D converter. The decoder accepts PCM data and expands it using a differential D/A converter. The output of the D/A is lowpass filtered 3400 Hz and sinX/X compensated by a differential switched capacitor filter. The signal is then filtered by an active RC filter to eliminate the outofband energy of the switched capacitor filter. The MC145480 PCM CodecFilter accepts a variety of clock formats, including Short Frame Sync, Long Frame Sync, IDL, and GCI timing environments. This device also maintains compatibility with Motorola's family of Telecommunication products, including the MC14LC5472 UInterface Transceiver, MC145474/75 S/TInterface Transceiver, MC145532 ADPCM Transcoder, MC145421/25 UDLT2, and MC3419/MC33120 SLIC. The MC145480 PCM CodecFilter utilizes CMOS due to its reliable lowpower performance and proven capability for complex analog/digital VLSI functions. Single 5 V Power Supply Typical Power Dissipation of 23 mW, PowerDown 0.01 mW FullyDifferential Analog Circuit Design for Lowest Noise Transmit BandPass and Receive LowPass Filters OnChip Active RC PreFiltering and PostFiltering MuLaw and ALaw Companding by Pin Selection OnChip Precision Reference Voltage (1.575 V) PushPull 300 Power Drivers with External Gain Adjust MC145536EVK is the Evaluation Kit that Also Includes the MC145532 ADPCM Transcoder
FSR + SHARED DAC + 1 SEQUENCE AND CONTROL 1.575 V REF 2.4 V REFERENCE BCLKR Mu/A PDI MCLK BCLKT FST + FREQ ADC TRANSMIT SHIFT REGISTER
A PCM CodecFilter is used for digitizing and reconstructing the human voice. These devices are used primarily for the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec is an acronym from ``COder'' for the analogtodigital converter (ADC) used to digitize voice, and ``DECoder'' for the digitaltoanalog converter (DAC) used for reconstructing voice. A codec is a single device that does both the ADC and DAC conversions. To digitize intelligible voice requires a signaltodistortion ratio of about 30 dB over a dynamic range of about 40 dB. This may be accomplished with a linear 13bit ADC and DAC, but will far exceed the required signaltodistortion ratio at larger amplitudes than 40 dB below the peak amplitude. This excess performance is at the expense of data per sample. Two methods of data reduction are implemented by compressing the 13bit linear scheme to companded pseudologarithmic 8bit schemes. The two companding schemes are: Mu255 Law, primarily in North America and Japan; and ALaw, primarily used in Europe. These companding schemes are accepted world wide. These companding schemes follow a segmented or ``piecewiselinear'' curve formatted as sign bit, three chord bits, and four step bits. For a given chord, all sixteen of the steps have the same voltage weighting. As the voltage of the analog input increases, the four step bits increment and carry to the three chord bits
which increment. When the chord bits increment, the step bits double their voltage weighting. This results in an effective resolution of six bits (sign + chord + four step bits) across 42 dB dynamic range (seven chords above 6 dB per chord). In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal's highest frequency component. Voice contains spectral energy above 3 kHz, but its absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a bandwidth of 3 kHz. This sampling requires a lowpass filter to limit the high frequency energy above 3 kHz from distorting the inband signal. The telephone line is also subject 50/60 Hz power line coupling, which must be attenuated from the signal by a highpass filter before the analogto digital converter. The digitaltoanalog conversion process reconstructs a staircase version of the desired inband signal, which has spectral images of the inband signal modulated about the sample frequency and its harmonics. These spectral images are called aliasing components, which need to be attenuated to obtain the desired signal. The lowpass filter used to attenuate these aliasing components is typically called a reconstruction or smoothing filter. The MC145480 PCM CodecFilter has the codec, both presampling and reconstruction filters, a precision voltage reference onchip, and requires no external components.
POWER SUPPLY VDD Positive Power Supply (Pin 6) This is the most positive power supply and is typically connected 5 V. This pin should be decoupled V SS with 0.1 µF ceramic capacitor. VSS Negative Power Supply (Pin 15) This is the most negative power supply and is typically connected 0 V. VAG Analog Ground Output (Pin 20) This output pin provides a midsupply analog ground regulated 2.4 V. This pin should be decoupled to VSS with 0.1 µF ceramic capacitor. All analog signal processing within this device is referenced to this pin. If the audio signals to be processed are referenced to V SS, then special precautions must be utilized to avoid noise between V SS and the VAG pin. Refer to the applications information in this document for more information. The VAG pin becomes high impedance when this device is in the powered down mode. CONTROL Mu/A Law Select (Pin 16) This pin controls the compression for the encoder and the expansion for the decoder. MuLaw companding is selected when this pin is connected to VDD and ALaw companding is selected when this pin is connected to VSS. PDI PowerDown Input (Pin 10) This pin puts the device into a low power dissipation mode when a logic 0 is applied. When this device is powered down, all of the clocks are gated off and all bias currents are turned off, which causes RO+, RO, PO, PO+, TG, VAG, and DT to become high impedance. The device will operate normally when a logic 1 is applied to this pin. The device goes through a powerup sequence when this pin is taken to a logic 1 state, which prevents the DT PCM output from going low impedance for at least two FST cycles. The filters must settle out before the DT PCM output or the RO+ or RO receive analog outputs will represent a valid analog signal. ANALOG INTERFACE TI+ Transmit Analog Input (NonInverting) (Pin 19) This is the noninverting input of the transmit input gain setting operational amplifier. This pin accommodates a differential to singleended circuit for the input gain setting op amp. This allows input signals that are referenced to the V SS pin to be level shifted to the VAG pin with minimum noise. This pin may be connected to the VAG pin for an inverting amplifier configuration if the input signal is already referenced to the VAG pin. The common mode range of the TI+ and TI pins is from V, to VDD minus 2 V. This is an FET gate input. Connecting both TI+ and TI pins V DD will
place this amplifier's output (TG) into a highimpedance state, thus allowing the TG pin to serve as a highimpedance input to the transmit filter. TI Transmit Analog Input (Inverting) (Pin 18) This is the inverting input of the transmit gain setting operational amplifier. Gain setting resistors are usually connected from this pin to TG and from this pin to the analog signal source. The common mode range of the TI+ and TI pins is from V to VDD 2 V. This is an FET gate input. Connecting both TI+ and TI pins to VDD will place this amplifier's output (TG) into a highimpedance state, thus allowing the TG pin to serve as a highimpedance input to the transmit filter. TG Transmit Gain (Pin 17) This is the output of the transmit gain setting operational amplifier and the input to the transmit bandpass filter. This op amp is capable of driving 2 k load. Connecting both TI+ and TI pins to VDD will place this amplifier's output (TG) into a highimpedance state, thus allowing the TG pin to serve as a highimpedance input to the transmit filter. All signals at this pin are referenced to the VAG pin. This pin is high impedance when the device is in the powered down mode. RO+ Receive Analog Output (NonInverting) (Pin 1) This is the noninverting output of the receive smoothing filter from the digitaltoanalog converter. This output is capable of driving 2 k load 1.575 V peak referenced to the VAG pin. This pin is high impedance when the device is in the powered down mode. RO Receive Analog Output (Inverting) (Pin 2) This is the inverting output of the receive smoothing filter from the digitaltoanalog converter. This output is capable of driving 2 k load 1.575 V peak referenced to the VAG pin. This pin is high impedance when the device is in the powered down mode. PI Power Amplifier Input (Pin 3) This is the inverting input to the PO amplifier. The non inverting input to the PO amplifier is internally tied to the VAG pin. The PI and PO pins are used with external resistors in an inverting op amp gain circuit to set the gain of the PO+ and PO pushpull power amplifier outputs. Connecting PI to VDD will power down the power driver amplifiers and the PO+ and PO outputs will be high impedance. PO Power Amplifier Output (Inverting) (Pin 4) This is the inverting power amplifier output, which is used to provide a feedback signal to the PI pin to set the gain of the pushpull power amplifier outputs. This pin is capable of driving a 300 load to PO+. The PO+ and PO outputs are differential (pushpull) and capable of driving a 300 load 3.15 V peak, which 6.3 V peaktopeak. The bias voltage and signal reference of this output is the VAG pin. The VAG
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