|Datasheet||Download MC145474P datasheet
The MC145557, MC145564, and MC145567 are all per channel PCM CodecFilters. These devices perform the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems. They are designed to operate in both synchronous and asynchronous applications and contain an onchip precision voltage reference. The MC145554 (MuLaw) and MC145557 (ALaw) are general purpose devices that are offered in 16pin packages. The MC145564 (MuLaw) and MC145567 (ALaw), offered in 20pin packages, add the capability of analog loopback and pushpull power amplifiers with adjustable gain. These devices have an input operational amplifier whose output is the input to the encoder section. The encoder section immediately lowpass filters the analog signal with an active RC filter to eliminate veryhighfrequency noise from being modulated down to the pass band by the switched capacitor filter. From the active RC filter, the analog signal is converted to a differential signal. From this point, all analog signal processing is done differentially. This allows processing of an analog signal that is twice the amplitude allowed by a singleended design, which reduces the significance of noise to both the inverted and noninverted signal paths. Another advantage of this differential design is that noise injected via the power supplies is a commonmode signal that is cancelled when the inverted and noninverted signals are recombined. This dramatically improves the power supply rejection ratio. After the differential converter, a differential switched capacitor filter band passes the analog signal from 3400 Hz before the signal is digitized by the differential compressing A/D converter. The decoder accepts PCM data and expands it using a differential D/A converter. The output of the D/A is lowpass filtered 3400 Hz and sinX/X compensated by a differential switched capacitor filter. The signal is then filtered by an active RC filter to eliminate the outofband energy of the switched capacitor filter. These PCM CodecFilters accept both longframe and shortframe industry standard clock formats. They also maintain compatibility with Motorola's family of TSACs and MC3419/MC34120 SLIC products. The MC145554/57/64/67 family of PCM CodecFilters utilizes CMOS due to its reliable lowpower performance and proven capability for complex analog/digital VLSI functions. MC145554/57 (16Pin Package) Fully Differential Analog Circuit Design for Lowest Noise Performance Specified for Extended Temperature Range + 85°C Transmit BandPass and Receive LowPass Filters OnChip Active RC PreFiltering and PostFiltering MuLaw Companding MC145554 ALaw Companding MC145557 OnChip Precision Voltage Reference (2.5 V) Typical Power Dissipation of 40 mW, Power Down MC145564/67 (20Pin Package) All of the Features of the MC145554/57 Plus: MuLaw Companding MC145564 ALaw Companding MC145567 PushPull Power Drivers with External Gain Adjust Analog Loopback
L SUFFIX CERAMIC PACKAGE CASE MC145554/57 P SUFFIX PLASTIC DIP CASE MC145554/57 DW SUFFIX SOG PACKAGE CASE 751G MC145554/57P SUFFIX PLASTIC DIP CASE MC145564/67 DW SUFFIX SOG PACKAGE CASE 751D MC145564/67
VBB GNDA VFRO VCC FSR DR BCLKR/ CLKSEL MCLKR/ PDN VFXI + VFXI GSX TSX FSX DX BCLKX MCLKX
+ RC ACTIVE LOWPASS FILTER 5POLE SC LOWPASS FILTER 3POLE HIGHPASS AND S/H COMP
VPI* RC ACTIVE LOWPASS FILTER 5POLE SC LOWPASS FILTER
A codecfilter is used for digitizing and reconstructing the human voice. These devices were developed primarily for the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec is an acronym from "COder" (for the A/D used to digitize voice) and "DECoder" (for the D/A used for reconstructing voice). A codec is a single device that does both the A/D and D/A conversions. To digitize intelligible voice requires a signaltodistortion ratio of about 30 dB over a dynamic range of about 40 dB. This can be accomplished with a linear 13bit A/D and D/A, but will far exceed the required signaltodistortion ratio at amplitudes greater than 40 dB below the peak amplitude. This excess performance is at the expense of data per sample. Methods of data reduction are implemented by compressing the 13bit linear scheme to companded 8bit schemes. There are two companding schemes used: Mu255 Law specifically in North America, and ALaw specifically in Europe. These companding schemes are accepted world wide. These companding schemes follow a segmented or "piecewiselinear" curve formatted as sign bit, three chord bits, and four step bits. For a given chord, all sixteen of the steps have the same voltage weighting. As the voltage of the analog input increases, the four step bits increment and carry to the three chord bits which increment. When the chord bits increment, the step bits double their voltage weighting. This results in an effective resolution of six bits (sign + chord + four step bits) across 42 dB dynamic range (seven chords above zero, 6 dB per chord). Tables 3 and 4 show the linear quantization levels to PCM words for the two companding schemes. In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal's highest frequency component. Voice contains spectral energy above 3 kHz, but its absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a bandwidth of 3 kHz. This sampling requires a lowpass filter to limit the high frequency energy above 3 kHz from distorting the inband signal. The telephone line is also subject 50/60 Hz power line coupling, which must be attenuated from the signal by a highpass filter before the A/D converter. The D/A process reconstructs a staircase version of the desired inband signal, which has spectral images of the in band signal modulated about the sample frequency and its harmonics. These spectral images, called aliasing components, need to be attenuated to obtain the desired signal. The lowpass filter used to attenuate these aliasing components is typically called a reconstruction or smoothing filter. The MC145554/57/64/67 PCM CodecFilters have the codec, both presampling and reconstruction filters, and a precision voltage reference onchip, and require no external components. DIGITAL
FSR Receive Frame Sync This an 8 kHz enable that must be synchronous with BCLK R. Following a rising FS R edge, a serial PCM word R is clocked by BCLK R into the receive data register. FS R also initiates a decode on the previous PCM word. In the absence FS X, the length of the FS R pulse is used to determine whether the I/O conforms to the Short Frame Sync or Long Frame Sync convention. DR Receive Digital Data Input BCLKR/CLKSEL Receive Data Clock and Master Clock Frequency Selector If this input is a clock, it must be between 128 kHz and 4.096 MHz, and synchronous with FSR. In synchronous applications this pin may be held at a constant level; then BCLKX is used as the data clock for both the transmit and receive sides, and this pin selects the assumed frequency of the master clock (see Table 1 in Functional Description). MCLKR/PDN Receive Master Clock and PowerDown Control Because of the shared DAC architecture used on these devices, only one master clock is needed. Whenever FSX is clocking, MCLK X is used to derive all internal clocks, and the MCLK R /PDN pin merely serves as a powerdown control. If MCLK R /PDN pin is held low or is clocked (and at least one of the frame syncs is present), the part is powered up. If this pin is held high, the part is powered down. X is absent but R is still clocking, the device goes into receive half channel mode, and MCLK R (if clocking) generates the internal clocks. MCLKX Transmit Master Clock This clock is used to derive the internal sequencing clocks; it must be 1.536 MHz, 1.544 MHz, or 2.048 MHz. BCLKX Transmit Data Clock BCLK X may be any frequency between 128 kHz and 4.096 MHz, but it should be synchronous with MCLKX. DX Transmit Digital Data Output This output is controlled FS X and BCLKX to output the PCM data word; otherwise this pin in a highimpedance state. FSX Transmit Frame Sync This an 8 kHz enable that must be synchronous with BCLK X. A rising FS X edge initiates the transmission of a
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