AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems

Category: Logic
Manufacture: Altera Corporation
Datasheet: Download this application note

Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems
November 2007, ver. 1.1
The SignalTap® II Embedded Logic Analyzer (ELA) is a system-level debugging tool that captures and displays real-time signals in a system-on-a-programmable-chip (SOPC) design. By using a SignalTap II ELA in systems generated by SOPC Builder, designers can observe the behavior of hardware (such as peripheral registers, memory buses, and other on-chip components) in response to software execution.
This application note explains how to use a SignalTap II ELA to monitor signals located inside a system module generated by the SOPC Builder. The examples described in this document use the standard hardware and count binary software. A simplified version of a block diagram of the system is shown in Figure 1. This system contains a Nios® II processor, an on-chip memory, and an interface to external DDR SDRAM memory, among other things. The count binary program counts from 0 to 0×FF repeatedly. Output of the counting process is displayed on the LEDs, the seven segment display, and the LCD. Four push buttons are used to control output to these devices. Figure 1. An Example SOPC Builder System
System Interconnect Fabric
(1) (2) (3) This is the external memory interface. These are the parallel I/O (PIO) internal registers. This is the on-chip memory interface.
Altera Corporation AN-323-1.1
Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems
This application note explains how to connect the SignalTap II Embedded Logic Analyzer to three different types of signals (see Figure 1) that are useful to monitor:
Signals connected to an external I/O interface, in this case an external SDRAM memory. Internal registers of a peripheral inside the system module, in this case the PIO. Avalon® interfaces between the System Interconnect Fabric logic and a peripheral inside the system module, in this case an on-chip memory.
This document does not discuss the contents of the standard design example, but you can explore the design in SOPC Builder and refer to the readme.txt in the design directory to gain a better understanding.
To complete the steps in this document, you need the following:
Quartus® II software, version 7.2 or higher Nios II Embedded Development Suite 7.2 or higher Nios II Development Kit, Cyclone® II, or Stratix® II Edition
The design files that accompany this application note are included in the examples directory installed with the Nios II Embedded Design Suite. The default location is: \\nios2eds\examples
Designing with SignalTap II and SOPC Builder Systems
The following steps guide you through opening a Quartus II project that includes an SOPC Builder-generated system module, and creating a SignalTap II ELA to analyze signals in the system.
Open and Generate the SOPC Builder System
1. Copy the entire folder for the Nios II standard example design for your particular board to a location where it can be edited. This folder is located in the following path:
If you are using Verilog as your primary HDL: //nios2eds/examples/verilog//standard

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