Flip Chip CSP Packages
Manufacture: ON Semiconductor
Datasheet: Download this application note
AND8081/D Flip Chip CSP Packages
Prepared by: Denise Thienpont ON Semiconductor Staff Engineer http://onsemi.com
Introduction to Chip Scale Packaging This application note provides guidelines for the use of Chip Scale Packages related to mounting devices to a PCB. Included is information on PCB layout for Systems Engineers, and manufacturing processes for Manufacturing Process Engineers. Package Overview
Flip Chip CSP "Package" Overview
Package Construction and Process Description
Chip Scale packages offered by ON Semiconductor represent the smallest footprint size since the package is the same size as the die. ON Semiconductor offers two types of CSPs, or bumped die Flip Chip CSP and Standard Bump. This application note covers only the Flip Chip CSPs with larger bumps. Flip Chip CSP bumped die are created by attaching 300 mm solder spheres to the I/O pads of the active side of the wafer. The I/O layout can either be peripheral or array. No redistribution layer is used. The 63/37 SnPb solder bumps allow compatibility of the package connections with standard surface mount technology pick and place and reflow processes and standard flip chip mounting systems. The larger solder bumps of the Flip Chip CSP requires no underfill to increase reliability performance. Devices designed with the smaller standard bumps generally have a peripheral pad layout and a tighter spacing than that of the Flip Chip CSPs. Underfill is recommended to increase board level solder joint reliability.
The Flip Chip CSP is a wafer level processing technique. Upon completion of standard wafer processing, a polymeric BCB passivation layer is applied to the wafer, leaving the bonding pads exposed. A sputtered thin film underbump Al/NiV/Cu metallization (UBM) is applied to the device bonding bonds to provide an interface between the die pad metallization and the solder bump. Solder spheres are placed on each exposed pad and reflowed to create an interconnection system ready for board assembly. Once the bumps are reflowed, wafers are electrically tested, laser marked, sawn into individual die, and packed in tape and reel, bumps down. A typical Flip Chip CSP is represented in Figure 1. Total device thickness will vary, depending on customer requirements.
625 - 675 mm 500 mm Pitch
290 - 340 mm Bump Diameter 210 - 270 mm 2.5 mm
Figure 1. Daisy Chain Flip Chip CSP
© Semiconductor Components Industries, LLC, 2003
August, 2003 - Rev. 0
Publication Order Number: AND8081/D
Printed Circuit Board Design
Recommended PCB Layout Table 1. PCB Assembly Recommendations
Parameter PCB Pad Size Pad Shape Pad Type Solder Mask Opening Solder Stencil Thickness Stencil Aperture Solder Flux Ratio Solder Paste Type Trace Finish Trace Width 500 mm Pitch 300 mm Solder Ball 250 mm )25 -0 Round NSMD 350 mm $25 125 mm 250 x 250 mm sq. 50/50 No Clean Type 3 or Finer OSP Cu 150 mm Max
Two types of land patterns are commonly used for surface mount packages non-solder mask defined (NSMD) and solder mask defined (SMD), Figure 2. With SMD configured pads, the solder mask covers the outside perimeter of the circular contact pads, thus limiting the solder attach to just the top surface of the exposed pads. With NSMD configured pads, there is a gap between the solder mask and the circular contact pad. NSMD pads are preferred due to better control of the copper etch process as compared with the solder mask etch process in the SMD pad definition. The solder bumps will attach to the NSMD pad wall as well as the pad surface, which provides additional mechanical strength and solder joint fatigue life. SMD pad definition introduces increased levels of stress near the solder mask overlap region which results in solder joint fatigue cracking in extreme temperature cycling conditions. The smaller NSMD pads also provide more room for escape routing on the PCB since they can be smaller in diameter than SMD pads.
PCB I/O Contacts Surface Finish Characteristics
Organic solderability preservative (OSP) pad finish is recommended for optimum solder joint reliability. Electroless nickel-immersion gold finish with gold thickness ranging from 0.05 0.127 mm may also be used, although solder joint integrity may suffer due to the presence of brittle gold/tin intermetallics. Hot Air Solder Leveled finish (HASL) is not recommended because the process does not give consistent solder volumes on each pad. Solder Assembly Recommendations
Surface mount assembly operations include printing solder paste onto the PCB.
Solder Paste Characteristics
Figure 2. NSMD vs. SMD
A copper layer thickness of less than 1 oz (30 mm) is recommended to maintain a maximum stand-off height and consequently maximum solder joint fatigue life. Micro-via pads should be NSMD to ensure adequate wetting area of the copper pad. A summary of recommended design parameters is found in Table 1.
Type 3 (25 45 mm powder), Type 4 (20 38 mm powder) or Type 5 (15 25 mm powder) ANSI/J-STD-005 compliant solder paste is suggested. No-clean solder paste is recommended. RMA or water soluble (OA) solder paste flux may also be used. Metal load range is from 85 90 wt%. Solder flux ratio should be 50/50 by volume.
Solder Stencil and Printing
Stainless steel, brass, or nickel plated stencils with laser cut or metal additive apertures are recommended. Five degree tapered walls are suggested for laser cut stencils to facilitate the release of the paste when the screen is removed from the PCB. Stencil thickness of 0.125 mm with openings approximately the same size as the substrate bond pads are recommended. It is highly recommended that the solder paste height, uniformity, registration and proper placement during the squeegee printing are monitored.