Dynamic Threshold for Advanced CMOS Logic

Category: Logic
Manufacture: Fairchild Semiconductor
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AN-680 Dynamic Threshold for Advanced CMOS Logic
Fairchild Semiconductor Application Note February 1990 Revised June 2001
Dynamic Threshold for Advanced CMOS Logic
Most users of digital logic are quite familiar with the threshold specifications found on family logic data sheets. Designers using products with TTL level input thresholds will see numbers like VIH = 2.0V and VIL = 0.8V. These threshold guarantees are static, a part's response to these levels during switching transients can be undesirable. Through the course of this paper the reader should gain an understanding for the difference between a static threshold and a dynamic threshold. This paper will also discuss how various products respond dynamically and how dynamic thresholds are tested and specified. Lastly, this paper will look at how FACT Quiet Series has addressed and specified dynamic threshold characteristics.
What Is a Dynamic Threshold?
If Fairchild Semiconductor were able to package its I.C.'s in "ideal" packages, then dynamic and static thresholds would be one and the same. However, packages are not "ideal" and have a finite amount of inductance associated with each signal lead. As will be shown later, it is the inductance in the power leads which is the primary reason for dynamic thresholds. To understand the phenomena of dynamic threshold, properties of ground bounce must first be examined. Figure 1 is a representation for a 74XX00 product which includes package inductance. Figure 2a shows an output pull-down making an HL/ZL transition. In discharging the load capacitor, a current IC equaling C*dv/dt flows into the chip. This current is approximated versus time in Figure 2b. The changing current, IC, generates a voltage across the ground inductor represented in Figure 2c. The equation L*di/dt provides the relationship of current and time with respect to a given inductor. It is the voltage across the ground inductor, commonly known as ground bounce, which causes static and dynamic thresholds to differ.
FIGURE 1. A Typical 2-Input Quad NAND Gate
FIGURE 2. Package Inductance Causes Ground Bounce
FACT, FACT Quiet Series, Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
2001 Fairchild Semiconductor Corporation
What Is a Dynamic Threshold?
(Continued) the input level does not necessarily induce a product failThe threshold of an IC is referenced to its internal ground. ure. The threshold must cross the input level for a period of Therefore, voltages induced on the ground inductor are time for a false switch to occur. (Figure 4 shows the voltage reflected directly as a change in threshold with respect to time relationship). Note that in the high speed technologies external ground. Figure 3 shows the effects of ground two things have come together, faster delays and output bounce on an input threshold. A problem area exists if edge rates. This translates to larger di/dt's and an ability to when the threshold is moving, the threshold crosses the react to narrower pulses. input voltage levels. However, having the threshold cross
FIGURE 3. Ground Bounce Changes Input Threshold VIL Noise Rejection
FIGURE 4. Device Speed Effects Noise Margins In the example discussed above, ground bounce was outlined as the cause for the threshold change. For bipolar TTL technologies, this is the only noise source of concern since the threshold is created by a VBE transistor stack referenced to ground. As VCC changes in a bipolar circuit, the threshold will change logarithmically as the currents in the transistors change. For example, a 1V change in VCC creates approximately a 34 mV shift in threshold. CMOS thresholds are set up as a percentage of VDD and track linearly with VDD changes. Therefore, a noise spike on VDD from an LH/ZH transition generates dynamic threshold characteristics which must be considered along with those of the HL/ZL edges. In this example let internal ground bounce to a 1V peak; the bipolar threshold will peak to approximately 2.5V. If we consider a TTL level static threshold for a CMOS device input of 1.5V, the following applies: ((VTH/VDD*(VDD - Vbounce) + 1.0V) = ((0.3*(4.0) + 1.0) = 2.2V. Consider a negative bounce of 1V on the internal VDD bus. The threshold delta for the bipolar product will be negligible, but the CMOS input threshold will change as follows: ((VTH/VDD *(VDD - Vbounce)) = (0.3*(4)) = 1.2V

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